參數(shù)資料
型號： LTC2435IGN
廠商： Linear Technology
文件頁數(shù)： 21/42頁
文件大?。?/td> 0K
描述： IC CONV A/D 20BIT DIFF 16-SSOP
標準包裝： 100
位數(shù)： 20
采樣率（每秒）： 15
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
轉換器數(shù)目： 2
功率耗散（最大）： 1mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-SSOP（0.154"，3.90mm 寬）
供應商設備封裝： 16-SSOP
包裝： 管件
輸入數(shù)目和類型： 1 個差分，雙極
LTC2435/LTC2435-1
28
24351fc
For more information www.linear.com/LTC2435
applicaTions inForMaTion
tion suggested earlier because they include the effect of
the actual second order input network together with the
nonlinear settling process of the input amplifiers. For
small CINvalues,thesettlingonIN+andIN–occursalmost
independently and there is little benefit in trying to match
the source impedance for the two pins.
Larger values of input capacitors (CIN > 0.01F) may be
required in certain configurations for anti-aliasing or gen-
eral input signal filtering. Such capacitors will average the
input sampling charge and the external source resistance
will see a quasi constant input differential impedance.
When FO = LOW (internal oscillator and 60Hz notch), the
typical differential input resistance is 22MΩ (LTC2435)
or 24MΩ (LTC2435-1) which will generate a +FS gain er-
ror of approximately 0.023ppm (LTC2435) or 0.021ppm
(LTC2435-1) for each ohm of source resistance driving
IN+ or IN–. For the LTC2435, when FO = HIGH (internal
oscillator and 50Hz notch), the typical differential input
resistance is 26MΩ which will generate a +FS gain error
of approximately 0.019ppm for each ohm of source resis-
tance driving IN+ or IN–. When FO is driven by an external
oscillatorwithafrequencyfEOSC(externalconversionclock
operation), the typical differential input resistance is 3.3
1012/fEOSCΩ and each ohm of source resistance driving
IN+ or IN– will result in 0.15 10–6 fEOSC ppm +FS gain
error. The effect of the source resistance on the two input
pins is additive with respect to this gain error. The typical
+FS and –FS errors as a function of the sum of the source
resistance seen by IN+ and IN– for large values of CIN are
shown in Figures 18 and 19.
In addition to this gain error, an offset error term may also
appear. The offset error is proportional to the mismatch
between the source impedance driving the two input
pins IN+ and IN– and with the difference between the
input and reference common mode voltages. While the
input drive circuit nonzero source impedance combined
with the converter average input current will not degrade
the INL performance, indirect distortion may result from
the modulation of the offset error by the common mode
component of the input signal. Thus, when using large
CIN capacitor values, it is advisable to carefully match the
source impedance seen by the IN+ and IN– pins. When
FO = LOW (internal oscillator and 60Hz notch), every 1Ω
mismatch in source impedance transforms a full-scale
common mode input signal into a differential mode input
signal of 0.023ppm. When FO = HIGH (internal oscillator
and 50Hz notch), every 1Ω mismatch in source imped-
ance transforms a full-scale common mode input signal
into a differential mode input signal of 0.02ppm. When FO
is driven by an external oscillator with a frequency fEOSC,
every1Ωmismatchinsourceimpedancetransformsafull-
scale common mode input signal into a differential mode
Figure 18. +FS Error vs RSOURCE at IN+ or IN– (Large CIN)
Figure 19. –FS Error vs RSOURCE at IN+ or IN– (Large CIN)
RSOURCE ()
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
+FS
ERROR
VARIATION
(ppm)
2435 F18
0
400
800
1200
1600
2000
VCC = 5V
VREF+ = 5V
VREF– = GND
VIN+ = 3.75V
VIN– = 1.25V
FO = GND
TA = 25°C
CIN = 1F, 10F
CIN = 0.01F
CIN = 0.1F
RSOURCE ()
100
90
80
70
60
50
40
30
20
10
0
–FS
ERROR
VARIATION
(ppm)
2435 F19
0
400
800
1200
1600
2000
VCC = 5V
VREF+ = 5V
VREF– = GND
VIN+ = 1.25V
VIN– = 3.75V
FO = GND
TA = 25°C
CIN = 1F, 10F
CIN = 0.01F
CIN = 0.1F
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