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參數(shù)資料
| 型號： | LTC2435CGN#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 17/42頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC DIFF I/REF 20BIT 16-SSOP |
| 標準包裝： | 2,500 |
| 位數(shù)： | 20 |
| 采樣率（每秒）： | 15 |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 1mW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
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LTC2435/LTC2435-1
24
24351fc
For more information www.linear.com/LTC2435
applicaTions inForMaTion
SCK will go LOW. Once CS goes HIGH (within the time
period defined above as tEOCtest), the internal pull-up is
activated. For a heavy capacitive load on the SCK pin,
the internal pull-up may not be adequate to return SCK
to a HIGH level before CS goes low again. This is not a
concern under normal conditions where CS remains LOW
after detecting EOC = 0. This situation is easily overcome
by adding an external 10k pull-up resistor to the SCK pin.
Internal Serial Clock, 2-Wire I/O,
Continuous Conversion
This timing mode uses a 2-wire, all output (SCK and SDO)
interface. The conversion result is shifted out of the device
by an internally generated serial clock (SCK) signal, see
Figure 13. CS may be permanently tied to ground, sim-
plifying the user interface or isolation barrier.
The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 1ms after VCC exceeds 2.2V. An internal
weak pull-up is active during the POR cycle; therefore, the
internal serial clock timing mode is automatically selected
if SCK is not externally driven LOW (if SCK is loaded such
that the internal pull-up cannot pull the pin HIGH, the
external SCK mode will be selected).
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1). Once the conversion is
complete, SCK and SDO go LOW (EOC = 0) indicating
the conversion has finished. The data output cycle begins
on the first rising edge of SCK and ends after the 24th
rising edge. Data is shifted out the SDO pin on each fall-
ing edge of SCK. The internally generated serial clock is
output to the SCK pin. This signal may be used to shift
the conversion result into external circuitry. EOC can be
latched on the first rising edge of SCK and the last bit of
the conversion result can be latched on the 24th rising
edge of SCK. After the 24th rising edge, SDO goes HIGH
(EOC = 1) indicating a new conversion is in progress.
SCK remains HIGH during the conversion.
Figure 13. Internal Serial Clock, Continuous Operation
SDO
SCK
(INTERNAL)
CS
LSB
MSB
SIG
BIT 5
BIT 0
BIT 19
BIT 18
BIT 20
BIT 21
BIT 22
EOC
BIT 23
DATA OUTPUT
CONVERSION
2435 F13
VCC
FO
REF+
REF–
SCK
IN+
IN–
SDO
GND
CS
2
14
3
4
13
5
6
12
1, 7, 8, 9, 10, 15, 16
11
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
2-WIRE
INTERFACE
1
F
2.7V TO 5.5V
LTC2435/
LTC2435-1
= 50Hz REJECTION (LTC2435)
= EXTERNAL OSCILLATOR
= 60Hz REJECTION (LTC2435)
= 50Hz/60Hz REJECTION (LTC2435-1)
VCC
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