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參數(shù)資料
型號(hào)： LTC2431CMS#TR
廠商： Linear Technology
文件頁數(shù)： 7/40頁
文件大?。?/td> 0K
描述： IC ADC 20BIT DIFFINPUT/REF10MSOP
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 20
采樣率（每秒）： 7.5
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 1mW
電壓電源： 單電源
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 10-TFSOP，10-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 10-MSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 1 個(gè)差分，雙極
配用： DC586A-ND - BOARD DELTA SIGMA ADC LTC2431
其它名稱： LTC2431CMSTR
LTC2430/LTC2431
15
24301f
Table 3. LTC2430/LTC2431 State Duration
State
Operating Mode
Duration
CONVERT
Internal Oscillator
FO = LOW
133ms, Output Data Rate
≤ 7.5 Readings/s
(60Hz Rejection)
FO = HIGH
160ms, Output Data Rate
≤ 6.2 Readings/s
(50Hz Rejection)
External Oscillator
FO = External Oscillator
20510/fEOSCs, Output Data Rate ≤ fEOSC/20510 Readings/s
with Frequency fEOSC kHz
(fEOSC/2560 Rejection)
SLEEP
As Long As CS = HIGH
DATA OUTPUT
Internal Serial Clock
FO = LOW/HIGH
As Long As CS = LOW But Not Longer Than 1.25ms
(Internal Oscillator)
(24 SCK cycles)
FO = External Oscillator with
As Long As CS = LOW But Not Longer Than 192/fEOSCms
Frequency fEOSC kHz
(24 SCK cycles)
External Serial Clock with
As Long As CS = LOW But Not Longer Than 24/fSCKms
Frequency fSCK kHz
(24 SCK cycles)
is HIGH or floating at power-up or during this transition, the
converter enters the internal SCK mode. If SCK is LOW at
power-up or during this transition, the converter enters the
external SCK mode.
Serial Data Output (SDO)
The serial data output pin, SDO, provides the result of the
last conversion as a serial bit stream (MSB first) during the
data output state. In addition, the SDO pin is used as an end
of conversion indicator during the conversion and sleep
states.
When CS is HIGH, the SDO driver is switched to a high
impedance state. This allows sharing the serial interface
with other devices. If CS is LOW during the convert or
sleep state, SDO will output EOC. If CS is LOW during the
conversion phase, the EOC bit appears HIGH on the SDO
pin. Once the conversion is complete, EOC goes LOW.
Chip Select Input (CS)
The active LOW chip select, CS, is used to test the
conversion status and to enable the data output transfer as
described in the previous sections.
In addition, the CS signal can be used to trigger a new
conversion cycle before the entire serial data transfer has
been completed. The converter (LTC2430 or LTC2431)
will abort any serial data transfer in progress and start a
new conversion cycle anytime a LOW-to-HIGH transition
is detected at the CS pin after the converter has entered the
data output state (i.e., after the first rising edge of SCK
occurs with CS = LOW).
Finally, CS can be used to control the free-running modes
of operation, see Serial Interface Timing Modes section.
Grounding CS will force the ADC to continuously convert
at the maximum output rate selected by FO.
SERIAL INTERFACE TIMING MODES
The LTC2430/LTC2431’s 3-wire interface is SPI and
MICROWIRE compatible. This interface offers several
flexible modes of operation. These include internal/exter-
nal serial clock, 2- or 3-wire I/O, single cycle conversion.
The following sections describe each of these serial inter-
face timing modes in detail. In all these cases, the
converter can use the internal oscillator (FO = LOW or FO
= HIGH) or an external oscillator connected to the FO pin.
Refer to Table 4 for a summary.
External Serial Clock, Single Cycle Operation
(SPI/MICROWIRE Compatible)
This timing mode uses an external serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 5.
APPLICATIO S I FOR ATIO
WU
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