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參數(shù)資料
型號: LTC2415IGN
廠商: Linear Technology
文件頁數(shù): 20/40頁
文件大?。?/td> 0K
描述: IC A/D CONV 24BIT MICRPWR 16SSOP
標準包裝: 100
位數(shù): 24
采樣率(每秒): 15
數(shù)據(jù)接口: MICROWIRE?,串行,SPI?
轉換器數(shù)目: 2
功率耗散(最大): 1mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.154",3.90mm 寬)
供應商設備封裝: 16-SSOP
包裝: 管件
輸入數(shù)目和類型: 1 個差分,雙極
LTC2415/LTC2415-1
27
sn2415 24151fs
APPLICATIO S I FOR ATIO
WU
U
Figure 18. LTC2415/LTC2415-1 Equivalent Analog Input Circuit
Figure 19. An RC Network at IN+ and IN
Figure 21. –FS Error vs RSOURCE at IN
+ or IN(Small CIN)
Figure 20. +FS Error vs RSOURCE at IN+ or IN(Small CIN)
IIN
VV
V
R
IIN
VV
V
R
I REF
VV
V
R
V
VR
I REF
VV
V
R
V
VR
where
AVG
IN
INCM
REFCM
EQ
AVG
IN
INCM
REFCM
EQ
AVG
REF
INCM
REFCM
EQ
IN
REF
EQ
AVG
REF
INCM
REFCM
EQ
IN
REF
EQ
+
+
() = +
() = +
() =
+
() =
+
+
05
15
05
15
05
2
.
::
.
./
.
V
REF
V
REF
VIN
IN
V
IN
R
M
INTERNAL OSCILLATOR
Hz Notch F
LOW
R
M
INTERNAL OSCILLATOR
Hz Notch F
HIGH
R
f
EXTERNAL OSCILLATOR
R
REF
REFCM
IN
INCM
EQ
O
EQ
O
EQ
EOSC
EQ
=
+
=
==
()
==
()
=
()
=
+
2
361
60
432
50
0 555 10
397
12
LTC2415
M
INTERNAL OSCILLATOR
Hz
Hz Notch F
LOW
O
50
60
/
=
() LTC2415-1
CIN
2415 F19
VINCM + 0.5VIN
RSOURCE
IN+
LTC2415/
LTC2415-1
CPAR
20pF
CIN
VINCM – 0.5VIN
RSOURCE
IN
CPAR
20pF
RSOURCE ()
1
10
100
1k
10k
100k
+FS
ERROR
(ppm
OF
V
REF
)
2415 F20
50
40
30
20
10
0
VCC = 5V
REF+ = 5V
REF = GND
IN+ = 5V
IN= 2.5V
FO = GND
TA = 25°C
CIN = 0.01F
CIN = 0.001F
CIN = 100pF
CIN = 0pF
RSOURCE ()
1
10
100
1k
10k
100k
FS
ERROR
(ppm
OF
V
REF
)
2415 F21
0
–10
–20
–30
–40
–50
VCC = 5V
REF+ = 5V
REF = GND
IN+ = GND
IN= 2.5V
FO = GND
TA = 25°C
CIN = 0.01F
CIN = 0.001F
CIN = 100pF
CIN = 0pF
VREF+
VIN+
VCC
RSW (TYP)
20k
ILEAK
VCC
ILEAK
VCC
RSW (TYP)
20k
CEQ
18pF
(TYP)
RSW (TYP)
20k
ILEAK
IIN+
VIN
IIN
IREF+
IREF
2415 F18
ILEAK
VCC
ILEAK
SWITCHING FREQUENCY
fSW = 76800Hz INTERNAL
OSCILLATOR (LTC2415)
(FO = LOW OR HIGH)
fSW = 69900Hz INTERNAL
OSCILLATOR (LTC2415-1)
(FO = LOW)
fSW = 0.5 fEOSC EXTERNAL OSCILLATOR
VREF
RSW (TYP)
20k
incomplete settling of the input signal sampling process
may result in gain and offset errors, but it will not degrade
the INL performance of the converter. Figure 18 shows the
mathematical expressions for the average bias currents
flowing through the IN+ and INpins as a result of the
sampling charge transfers when integrated over a sub-
stantial time period (longer than 64 internal clock cycles).
The effect of this input dynamic current can be analyzed
using the test circuit of Figure 19. The CPAR capacitor
includes the LTC2415/LTC2415-1 pin capacitance (5pF
typical) plus the capacitance of the test fixture used to
obtain the results shown in Figures 20 and 21. A careful
implementation can bring the total input capacitance (CIN
+ CPAR) closer to 5pF thus achieving better performance
than the one predicted by Figures 20 and 21. For simplic-
ity, two distinct situations can be considered.
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