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參數(shù)資料
| 型號(hào)： | LTC2415IGN#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 19/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC A/D CONV 24BIT MICRPWR 16SSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 15 |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 1mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個(gè)差分，雙極 |
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LTC2415/LTC2415-1
26
sn2415 24151fs
APPLICATIO S I FOR ATIO
WU
U
LTC2415-1 pins may severely disturb the analog to digital
conversion process. Undershoot and overshoot can oc-
cur because of the impedance mismatch at the converter
pin when the transition time of an external control signal
is less than twice the propagation delay from the driver to
LTC2415/LTC2415-1. For reference, on a regular FR-4
board, signal propagation velocity is approximately
183ps/inch for internal traces and 170ps/inch for surface
traces. Thus, a driver generating a control signal with a
minimum transition time of 1ns must be connected to the
converter pin through a trace shorter than 2.5 inches. This
problem becomes particularly difficult when shared con-
trol lines are used and multiple reflections may occur. The
solution is to carefully terminate all transmission lines
close to their characteristic impedance.
Parallel termination near the LTC2415/LTC2415-1 pins
will eliminate this problem but will increase the driver
power dissipation. A series resistor between 27
and56
placed near the driver or near the LTC2415/LTC2415-1
pins will also eliminate this problem without additional
power dissipation. The actual resistor value depends upon
the trace impedance and connection topology.
An alternate solution is to reduce the edge rate of the
control signals. It should be noted that using very slow
edges will increase the converter power supply current
during the transition time. The multiple ground pins used
in this package configuration, as well as the differential
input and reference architecture, reduce substantially the
converter’s sensitivity to ground currents.
Particular attention must be given to the connection of the
FO signal when the LTC2415/LTC2415-1 are used with an
external conversion clock. This clock is active during the
conversion time and the normal mode rejection provided
by the internal digital filter is not very high at this fre-
quency. A normal mode signal of this frequency at the
converter reference terminals may result into DC gain and
INL errors. A normal mode signal of this frequency at the
converter input terminals may result into a DC offset error.
Such perturbations may occur due to asymmetric capaci-
tive coupling between the FO signal trace and the converter
input and/or reference connection traces. An immediate
solution is to maintain maximum possible separation
between the FO signal trace and the input/reference sig-
nals. When the FO signal is parallel terminated near the
converter, substantial AC current is flowing in the loop
formed by the FO connection trace, the termination and the
ground return path. Thus, perturbation signals may be
inductively coupled into the converter input and/or refer-
ence. In this situation, the user must reduce to a minimum
the loop area for the FO signal as well as the loop area for
the differential input and reference connections.
Driving the Input and Reference
The input and reference pins of the LTC2415/LTC2415-1
converters are directly connected to a network of sampling
capacitors. Depending upon the relation between the
differential input voltage and the differential reference
voltage, these capacitors are switching between these
four pins transferring small amounts of charge in the
process. A simplified equivalent circuit is shown in
Figure 18.
For a simple approximation, the source impedance RS
driving an analog input pin (IN+, IN–, REF+ or REF–) can be
considered to form, together with RSW and CEQ (see
Figure 18), a first order passive network with a time
constant
τ = (RS + RSW) CEQ. The converter is able to
sample the input signal with better than 1ppm accuracy if
the sampling period is at least 14 times greater than the
input circuit time constant
τ. The sampling process on the
four input analog pins is quasi-independent so each time
constant should be considered by itself and, under worst-
case circumstances, the errors may add.
When using the internal oscillator (FO = LOW or HIGH), the
LTC2415’s front-end switched-capacitor network is clocked
at 76800Hz corresponding to a 13
s sampling period and
the LTC2415-1’s front end is clocked at 69900Hz corre-
sponding to 14.2
s. Thus, for settling errors of less than
1ppm, the driving source impedance should be chosen
such that
τ ≤ 13s/14 = 920ns (LTC2415) and τ <14.2s/
14 = 1.01
s (LTC2415-1).. When an external oscillator of
frequency fEOSC is used, the sampling period is 2/fEOSC
and, for a settling error of less than 1ppm,
τ ≤ 0.14/fEOSC.
Input Current
If complete settling occurs on the input, conversion re-
sults will be unaffected by the dynamic input current. An
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