參數(shù)資料
型號(hào): LTC2413IGN
廠商: LINEAR TECHNOLOGY CORP
元件分類: ADC
英文描述: 24-Bit No Latency ADC, with Simultaneous 50Hz/60Hz Rejection
中文描述: 1-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO16
封裝: 0.150 INCH, PLASTIC, SSOP-16
文件頁(yè)數(shù): 27/44頁(yè)
文件大?。?/td> 454K
代理商: LTC2413IGN
LTC2413
27
sn2413 2413fs
APPLICATIU
W
U
U
Reference Current
In a similar fashion, the LTC2413 samples the differential
reference pins REF
+
and REF
transfering small amount of
charge to and from the external driving circuits, thus
produces a dynamic reference current. This current does
not change the converter offset but it may degrade the gain
and INL performance. The effect of this current can be
analyzed in the same two distinct situations.
For relatively small values of the external reference capaci-
tors (C
REF
< 0.01
μ
F), the voltage on the sampling capacitor
settles almost completely and relatively large values for
the source impedance result in only small errors. Such
values for C
REF
will deteriorate the converter offset and
gain performance without significant benefits of reference
filtering and the user is advised to avoid them.
Larger values of reference capacitors (C
REF
> 0.01
μ
F) may
be required as reference filters in certain configurations.
Such capacitors will average the reference sampling charge
and the external source resistance will see a quasi con-
stant reference differential impedance. When internal os-
cillator is used (F
O
= LOW), the typical differential input
resistance is 1.43M
which will generate a gain error of
approximately 0.35ppm for each ohm of source resis-
tance driving REF
+
or REF
. When F
O
is driven by an
external oscillator with a frequency f
EOSC
(external conver-
sion clock operation), the typical differential reference
resistance is 0.20 10
12
/f
EOSC
and each ohm of source
resistance drving REF
+
or REF
will result in
2.47 10
–6
f
EOSC
ppm gain error. The effect of the source
resistance on the two reference pins is additive with
respect to this gain error. The typical +FS and –FS errors
for various combinations of source resistance seen by the
REF
+
and REF
pins and external capacitance C
REF
con-
nected to these pins are shown in Figures 23, 24, 25
and26.
In addition to this gain error, the converter INL perfor-
mance is degraded by the reference source impedance.
When internal oscillator is used(F
O
= LOW), every 100
of
source impedance driving REF
+
or REF
translates into
about 1.2ppm additional INL error. When F
O
is driven by
an external oscillator with a frequency f
EOSC
, every 100
of source resistance driving REF
+
or REF
translates into
about 8.73 10
–6
f
EOSC
ppm additional INL error.
Figure 20. +FS Error vs R
SOURCE
at IN
+
or IN
(Large C
IN
)
Figure 21. –FS Error vs R
SOURCE
at IN
+
or IN
(Large C
IN
)
Figure 22. Offset Error vs Common Mode Voltage
(V
INCM
= IN
+
= IN
) and Input Source Resistance Imbalance
(
R
IN
= R
SOURCEIN
+ – R
SOURCEIN
–) for Large C
IN
Values (C
IN
1
μ
F)
R
SOURCE
(
)
0 100 200 300 400 500 600 700 800 9001000
+
R
)
2413 F19
300
240
180
120
60
0
V
CC
= 5V
REF
+
= 5V
REF
= GND
IN
+
= 3.75V
IN
= 1.25V
F
O
= GND
T
A
= 25
°
C
C
IN
= 0.01
μ
F
C
IN
= 0.1
μ
F
C
IN
= 1
μ
F, 10
μ
F
R
SOURCE
(
)
0 100 200 300 400 500 600 700 800 9001000
R
)
2413 F21
0
–60
–120
–180
–240
–300
V
CC
= 5V
REF
= 5V
REF
= GND
IN
+
= 1.25V
IN
= 3.75V
F
O
= GND
T
A
= 25
°
C
C
IN
= 0.01
μ
F
C
IN
= 0.1
μ
F
C
IN
= 1
μ
F, 10
μ
F
V
INCM
(V)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
O
R
)
2413 F22
120
100
80
60
40
20
0
–20
–40
–60
–80
–100
–120
F
O
= GND
T
A
= 25
°
C
R
SOURCEIN
– = 500
C
IN
F
V
= 5V
REF
+
= 5V
REF
= GND
IN
+
= IN
= V
INCM
A:
R
IN
= +400
B:
R
IN
= +200
C:
R
IN
= +100
D:
R
IN
= 0
E:
R
IN
= –100
F:
R
IN
= –200
G:
R
IN
= –400
A
B
C
D
E
F
G
相關(guān)PDF資料
PDF描述
LTC2413 2.7V to 5.5V Simultaneous 50Hz/60Hz Rejection Micropower Differential Σ△ Analog to Digital Converter(2.7V ~5.5V,微功耗,24位差分Σ△串行模數(shù)轉(zhuǎn)換器)
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