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參數(shù)資料
| 型號(hào)： | LTC2412CGN#TR |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 11/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CONV A/D 24B 2CH DIFF 16-SSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 7.5 |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 1mW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個(gè)差分，雙極 |
| 配用： | DC746A-ND - BOARD DELTA SIGMA ADC LTC2412 |
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LTC2412
19
2412f
APPLICATIO S I FOR ATIO
WU
U
Figure 7. External Serial Clock, CS = 0 Operation (2-Wire)
EOC
BIT 31
SDO
SCK
(EXTERNAL)
CS
MSB
SIG
CH0/CH1
BIT 0
LSB24
BIT 5
BIT 27
BIT 26
BIT 28
BIT 29
BIT 30
DATA OUTPUT
CONVERSION
2412 F07
CONVERSION
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
VCC
VCC
FO
REF+
SCK
CH1+
CH1–
SDO
GND
CS
114
2
3
13
6
7
12
8, 9, 10, 15, 16
11
REFERENCE
VOLTAGE
0.1V TO VCC
CH0+
CH0–
4
5
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
1
F
2.7V TO 5.5V
LTC2412
2-WIRE
INTERFACE
REF–
typically 1ms after VCC exceeds 2V. The level applied to
SCK at this time determines if SCK is internal or external.
SCK must be driven LOW prior to the end of POR in order
to enter the external serial clock timing mode.
Since CS is tied LOW, the end-of-conversion (EOC) can be
continuously monitored at the SDO pin during the convert
and sleep states. EOC may be used as an interrupt to an
external controller indicating the conversion result is
ready. EOC = 1 while the conversion is in progress and
EOC = 0 once the conversion ends. On the falling edge of
EOC, the conversion result is loaded into an internal static
shift register. Data is shifted out the SDO pin on each
falling edge of SCK enabling external circuitry to latch data
on the rising edge of SCK. EOC can be latched on the first
rising edge of SCK. On the 32nd falling edge of SCK, SDO
goes HIGH (EOC = 1) indicating a new conversion has
begun.
Internal Serial Clock, Single Cycle Operation
This timing mode uses an internal serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 8.
In order to select the internal serial clock timing mode, the
serial clock pin (SCK) must be floating (Hi-Z) or pulled
HIGH prior to the falling edge of CS. The device will not
enter the internal serial clock mode if SCK is driven LOW
on the falling edge of CS. An internal weak pull-up resistor
is active on the SCK pin during the falling edge of CS;
therefore, the internal serial clock timing mode is auto-
matically selected if SCK is not externally driven.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state.
When testing EOC, if the conversion is complete (EOC = 0),
the device will exit the sleep state during the EOC test. In
order to allow the device to return to the low power sleep
state, CS must be pulled HIGH before the first rising edge
of SCK. In the internal SCK timing mode, SCK goes HIGH
and the device begins outputting data at time tEOCtest after
the falling edge of CS (if EOC = 0) or tEOCtest after EOC goes
LOW (if CS is LOW during the falling edge of EOC). The
value of tEOCtest is 23s if the device is using its internal
oscillator (F0 = logic LOW or HIGH). If FO is driven by an
external oscillator of frequency fEOSC, then tEOCtest is
3.6/fEOSC. If CS is pulled HIGH before time tEOCtest, the
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