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參數(shù)資料
| 型號： | LTC2412 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 16-Bit Universal Bus Driver With 3-State Outputs 48-SSOP -40 to 85 |
| 中文描述： | 2路差分輸入24位ADC的無延遲局副局長 |
| 文件頁數(shù)： | 10/36頁 |
| 文件大?。?/td> | 409K |
| 代理商： | LTC2412 |
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LTC2412
10
2412f
V
CC
(Pin 1):
Positive Supply Voltage. Bypass to GND with
a 10
μ
F tantalum capacitor in parallel with 0.1
μ
F ceramic
capacitor as close to the part as possible.
REF
+
(Pin 2), REF
–
(Pin 3):
Differential Reference Input.
The voltage on these pins can have any value between GND
and V
CC
as long as the reference positive input, REF
+
, is
maintained more positive than the reference negative
input, REF
–
, by at least 0.1V.
CH0
+
(Pin 4):
Positive Input for Differential Channel 0.
CH0
–
(Pin 5):
Negative Input for Differential Channel 0.
CH1
+
(Pin 6):
Positive Input for Differential Channel 1.
CH1
–
(Pin 7):
Negative Input for Differential Channel 1.
The voltage on these four analog inputs (Pins 4 to 7) can
have any value between GND and V
CC
. Within these limits
the converter bipolar input range (V
IN
= IN
+
– IN
–
) extends
from –0.5 (V
REF
) to 0.5 (V
REF
). Outside this input range
the converter produces unique overrange and underrange
output codes.
GND (Pins 8, 9, 10, 15, 16):
Ground. Multiple ground pins
internally connected for optimum ground current flow and
V
CC
decoupling. Connect each one of these pins to a ground
plane through a low impedance connection. All five pins must
be connected to ground for proper operation.
CS (Pin 11):
Active LOW Digital Input. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the Data Output transfer aborts the data transfer
and starts a new conversion.
SDO (Pin 12):
Three-State Digital Output. During the Data
Output period, this pin is used as serial data output. When
the chip select CS is HIGH (CS = V
CC
) the SDO pin is in a
high impedance state. During the Conversion and Sleep
periods, this pin is used as the conversion status output.
The conversion status can be observed by pulling CS LOW.
SCK (Pin 13):
Bidirectional Digital Clock Pin. In Internal
Serial Clock Operation mode, SCK is used as digital output
for the internal serial interface clock during the Data
Output period. In External Serial Clock Operation mode,
SCK is used as digital input for the external serial interface
clock during the Data Output period. A weak internal pull-
up is automatically activated in Internal Serial Clock Op-
eration mode. The Serial Clock Operation mode is deter-
mined by the logic level applied to the SCK pin at power up
or during the most recent falling edge of CS.
PIU
TYPICAL PERFOR AU
TEMPERATURE (
°
C)
–45
0
S
μ
A
1
3
4
5
–15
15
30
90
2412 G39
2
–30
0
45
60
75
6
V
CC
= 5.5V
V
CC
= 2.7V
V
CC
= 5V
V
CC
= 3V
F
= GND
CS = V
SCK = NC
SDO = NC
Sleep Mode Current
vs Temperature
OUTPUT DATA RATE (READINGS/SEC)
0
100
S
μ
A
200
400
500
600
60 70 80 90
1000
2412 G38
300
10
20
30
40
50
100
700
800
900
V
REF
= V
CC
IN
+
= GND
IN
–
= GND
SCK = NC
SDO = NC
CS = GND
F
O
= EXT OSC
T
A
= 25
°
C
V
CC
= 5V
V
CC
= 3V
TEMPERATURE (
°
C)
–45
C
μ
A
200
210
220
75
2412 G37
190
180
160
–15
15
45
–30
90
0
30
60
170
240
230
V
CC
= 5.5V
V
CC
= 2.7V
V
CC
= 3V
V
CC
= 5V
F
= GND
CS = GND
SCK = NC
SDO = NC
Conversion Current
vs Output Data Rate
Conversion Current
vs Temperature
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