參數(shù)資料
型號(hào): LTC2411
廠商: Linear Technology Corporation
元件分類: ADC
英文描述: 2.7V to 5.5V Micropower 24-Bit Differential Σ△ Analog to Digital Converter(2.7V ~5.5V,微功耗,24位差分Σ△串行模數(shù)轉(zhuǎn)換器)
中文描述: 2.7V至5.5V微功耗24位差分Σ△模數(shù)轉(zhuǎn)換器(2.7?5.5V的,微功耗,24位差分Σ△串行模數(shù)轉(zhuǎn)換器)
文件頁(yè)數(shù): 10/24頁(yè)
文件大?。?/td> 268K
代理商: LTC2411
LTC2411
10
on the rising edge of the 32nd SCK pulse. On the falling
edge of the 32nd SCK pulse, SDO goes HIGH indicating the
initiation of a new conversion cycle. This bit serves as EOC
(Bit 31) for the next conversion cycle. Table 2 summarizes
the output data format.
As long as the voltage on the IN
+
and IN
pins is maintained
within the –0.3V to (V
CC
+ 0.3V) absolute maximum
operating range, a conversion result is generated for any
differential input voltage V
IN
from –FS = –0.5 V
REF
to
+FS = 0.5 V
REF
. For differential input voltages greater than
+FS, the conversion result is clamped to the value corre-
sponding to the +FS + 1LSB. For differential input voltages
below –FS, the conversion result is clamped to the value
corresponding to –FS – 1LSB.
Frequency Rejection Selection (F
O
)
The LTC2411 internal oscillator provides better than 110dB
normal mode rejection at the line frequency and all its
harmonics for 50Hz
±
2% or 60Hz
±
2%. For 60Hz rejec-
tion, F
O
should be connected to GND while for 50Hz
rejection the F
O
pin should be connected to V
CC
.
The selection of 50Hz or 60Hz rejection can also be made
by driving F
O
to an appropriate logic level. A selection
change during the sleep or data output states will not
disturb the converter operation. If the selection is made
during the conversion state, the result of the conversion in
progress may be outside specifications but the following
conversions will not be affected.
When a fundamental rejection frequency different from
50Hz or 60Hz is required or when the converter must be
Table 2. LTC2411 Output Data Format
Differential Input Voltage
V
IN
*
V
IN
*
0.5 V
REF
**
0.5 V
REF
** – 1LSB
0.25 V
REF
**
0.25 V
REF
** – 1LSB
0
–1LSB
Bit 31
EOC
0
0
Bit 30
DMY
0
0
Bit 29
SIG
1
1
Bit 28
MSB
1
0
Bit 27
Bit 26
Bit 25
Bit 0
0
1
0
1
0
1
0
1
0
0
0
0
1
1
0
0
1
0
0
1
0
1
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
1
0
1
–0.25 V
REF
**
–0.25 V
REF
** – 1LSB
–0.5 V
REF
**
V
IN
* < –0.5 V
REF
**
*The differential input voltage V
IN
= IN
+
– IN
.
**The differential reference voltage V
REF
= REF
+
– REF
.
0
0
0
0
0
0
1
1
1
0
0
1
0
1
0
1
0
0
0
0
0
0
1
0
0
1
0
1
0
1
0
1
Figure 3. Output Data Timing
APPLICATIU
W
U
U
MSB
SIG
“0”
1
2
3
4
5
26
27
32
BIT 0
BIT 27
BIT 5
LSB
24
BIT 28
BIT 29
BIT 30
SDO
SCK
CS
EOC
BIT 31
SLEEP
DATA OUTPUT
CONVERSION
2411 F03
Hi-Z
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