參數(shù)資料
型號(hào)： LTC2410
廠商： Linear Technology Corporation
英文描述： 20-Bit Universal Bus Driver With 3-State Outputs 56-SSOP -40 to 85
中文描述： 24位無(wú)與差分輸入和差分ADC的參考延遲
文件頁(yè)數(shù)： 11/44頁(yè)
文件大?。?/td> 778K
代理商： LTC2410
LTC2410
11
synchronized with an outside source, the LTC2410 can
operate with an external conversion clock. The converter
automatically detects the presence of an external clock
signal at the F
O
pin and turns off the internal oscillator. The
frequency f
EOSC
of the external signal must be at least
2560Hz (1Hz notch frequency) to be detected. The exter-
nal clock signal duty cycle is not significant as long as the
minimum and maximum specifications for the high and
low periods t
HEO
and t
LEO
are observed.
While operating with an external conversion clock of a
frequency f
EOSC
, the LTC2410 provides better than 110dB
normal mode rejection in a frequency range f
EOSC
/2560
±
4% and its harmonics. The normal mode rejection as a
function of the input frequency deviation from f
EOSC
/2560
is shown in Figure 4.
Whenever an external clock is not present at the F
O
pin the
converter automatically activates its internal oscillator and
enters the Internal Conversion Clock mode. The LTC2410
operation will not be disturbed if the change of conversion
clock source occurs during the sleep state or during the
data output state while the converter uses an external
serial clock. If the change occurs during the conversion
state, the result of the conversion in progress may be
outside specifications but the following conversions will
not be affected. If the change occurs during the data output
state and the converter is in the Internal SCK mode, the
serial clock duty cycle may be affected but the serial data
stream will remain valid.
Table 3 summarizes the duration of each state and the
achievable output data rate as a function of F
O
.
SERIAL INTERFACE PINS
The LTC2410 transmits the conversion results and re-
ceives the start of conversion command through a syn-
chronous 3-wire interface. During the conversion and
sleep states, this interface can be used to assess the
converter status and during the data output state it is used
to read the conversion result.
Table 3. LTC2410 State Duration
State
CONVERT
Operating Mode
Internal Oscillator
Duration
133ms, Output Data Rate
≤
7.5 Readings/s
F
O
= LOW
(60Hz Rejection)
F
O
= HIGH
(50Hz Rejection)
F
O
= External Oscillator
with Frequency f
EOSC
kHz
(f
EOSC
/2560 Rejection)
160ms, Output Data Rate
≤
6.2 Readings/s
External Oscillator
20510/f
EOSC
s, Output Data Rate
≤
f
EOSC
/20510 Readings/s
SLEEP
DATA OUTPUT
As Long As CS = HIGH Until CS = LOW and SCK
As Long As CS = LOW But Not Longer Than 1.67ms
(32 SCK cycles)
As Long As CS = LOW But Not Longer Than 256/f
EOSC
ms
(32 SCK cycles)
As Long As CS = LOW But Not Longer Than 32/f
SCK
ms
(32 SCK cycles)
Internal Serial Clock
F
O
= LOW/HIGH
(Internal Oscillator)
F
O
= External Oscillator with
Frequency f
EOSC
kHz
External Serial Clock with
Frequency f
SCK
kHz
Figure 4. LTC2410 Normal Mode Rejection When
Using an External Oscillator of Frequency f
EOSC
APPLICATIU
W
U
U
DIFFERENTIAL INPUT SIGNAL FREQUENCY
DEVIATION FROM NOTCH FREQUENCY f
EOSC
/2560(%)
–12
–8
–4
0
4
8
12
N
2410 F04
–80
–85
–90
–95
–100
–105
–110
–115
–120
–125
–130
–135
–140
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