參數(shù)資料
型號: LTC2400C
廠商: LINEAR TECHNOLOGY CORP
元件分類: ADC
英文描述: 24-Bit uPower No Latency ADC in SO-8
中文描述: 1-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO8
封裝: 0.150 INCH, PLASTIC, SO-8
文件頁數(shù): 20/40頁
文件大?。?/td> 455K
代理商: LTC2400C
20
LTC2400
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1). Once the conversion is
complete, SCK and SDO go LOW (EOC = 0) indicating the
conversion has finished and the device has entered the
low power sleep state. The part remains in the sleep state
a minimum amount of time (1/2 the internal SCK period)
then immediately begins outputting data. The data output
cycle begins on the first rising edge of SCK and ends after
the 32nd rising edge. Data is shifted out the SDO pin on
each falling edge of SCK. The internally generated serial
clock is output to the SCK pin. This signal may be used
to shift the conversion result into external circuitry. EOC
can be latched on the first rising edge of SCK and the last
bit of the conversion result can be latched on the 32nd
rising edge of SCK. After the 32nd rising edge, SDO goes
HIGH (EOC = 1) indicating a new conversion is in progress.
SCK remains HIGH during the conversion.
Internal Serial Clock, Autostart Conversion
This timing mode is identical to the internal serial clock,
2-wire I/O described above with one additional feature.
Instead of grounding CS, an external timing capacitor is
tied to CS.
While the conversion is in progress, the CS pin is held
HIGH by an internal weak pull-up. Once the conversion is
complete, the device enters the low power sleep state and
an internal 25nA current source begins discharging the
capacitor tied to CS, see Figure 11. The time the converter
spends in the sleep state is determined by the value of the
external timing capacitor, see Figures 12 and 13. Once the
voltage at CS falls below an internal threshold (
1.4V), the
device automatically begins outputting data. The data
output cycle begins on the first rising edge of SCK and
ends on the 32nd rising edge. Data is shifted out the SDO
APPLICATIO
S I
N
FOR
ATIO
U
W
U
SDO
Hi-Z
Hi-Z
SCK
(INTERNAL)
CS
V
CC
GND
2400 F11
V
CC
F
O
V
REF
SCK
V
IN
SDO
GND
C
EXT
CS
V
REF
0.1V TO V
CC
V
IN
–0.12V
REF
TO 1.12V
REF
1
μ
F
2.7V TO 5.5V
LTC2400
BIT 0
SIG
BIT 29
BIT 30
SLEEP
DATA OUTPUT
CONVERSION
CONVERSION
EOC
BIT 31
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
V
CC
Figure 11. Internal Serial Clock, Autostart Operation
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