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參數(shù)資料
| 型號： | LTC2391IUK-16#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 20/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16B SER/PAR 250KSPS 48QFN |
| 標準包裝： | 52 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 250k |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 125mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 48-QFN-EP（7x7） |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
| 配用： | DC1500A-C-ND - BOARD SAR ADC LTC2391-16 |
LTC2391-16
5
239116fa
TIMING CHARACTERISTICS The l denotes the specications which apply over the full operating temperature
range, otherwise specications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fSMPL
Sampling Frequency
l
250
ksps
tCONV
Conversion Time
l
2500
ns
tACQ
Acquisition Time
l
1485
ns
t4
CNVST Low Time
l
20
ns
t5
CNVST High Time
l
250
ns
t6
CNVST↓ to BUSY Delay
CL = 15pF
l
15
ns
t7
RESET Pulse Width
l
5ns
t8
SCLK Period
(Note 9)
l
12.5
ns
t9
SCLK High Time
l
4ns
t10
SCLK Low Time
l
4ns
tr, tf
SCLK Rise and Fall Times
(Note 10)
1
μs
t11
SDIN Setup Time
l
2ns
t12
SDIN Hold Time
l
1ns
t13
SDOUT Delay After SCLK↑
CL = 15pF
l
28
ns
t14
SDOUT Delay After CS↓
l
8ns
t15
CS↓ to SCLK Setup Time
l
20
ns
t16
Data Valid to BUSY↓
l
1ns
t17
Data Access Time after RD↓ or BYTESWAP↑
l
10
ns
t18
Bus Relinquish Time
l
10
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground.
Note 3: When these pin voltages are taken below ground or above
AVP, DVP or OVP, they will be clamped by internal diodes. This product can
handle input currents up to 100mA below ground or above AVP, DVP or
OVP without latchup.
Note 4: AVP = DVP = OVP = 5V, fSMPL = 250ksps, external reference equal
to 4.096V unless otherwise noted.
Note 5: Recommended operating conditions.
Note 6: Integral nonlinearity is dened as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: Bipolar zero error is the offset voltage measured from –0.5LSB
when the output code ickers between 0000 0000 0000 0000 and 1111
1111 1111 1111. Bipolar full-scale error is the worst-case of –FS or +FS
untrimmed deviation from ideal rst and last code transitions and includes
the effect of offset error.
Note 8: All specications in dB are referred to a full-scale ±4.096V input
with a 4.096V reference voltage.
Note 9: t13 of 8ns maximum allows a shift clock frequency up to
2 (t13 + tSETUP) for falling edge capture with 50% duty cycle and up to
80MHz for rising capture. tSETUP is the set-up time of the receiving logic.
Note 10: Guaranteed by design.
Note 11: Temperature coefcient is calculated by dividing the maximum
change in output voltage by the specied temperature range.
4V
0.5V
50%
239116F01
0.5V
4V
0.5V
4V
tDELAY
tWIDTH
tDELAY
Figure 1. Voltage Levels for Timing Specications
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