參數(shù)資料
型號(hào)： LTC2391CLX-16#PBF
廠商： LINEAR TECHNOLOGY CORP
元件分類(lèi)： ADC
英文描述： SUCCESSIVE APPROXIMATION ADC, PQFP48
封裝： 7 X 7 MM, LEAD FREE, PLASTIC, MS-026, LQFP-48
文件頁(yè)數(shù)： 6/24頁(yè)
文件大?。?/td> 286K
代理商： LTC2391CLX-16#PBF
LTC2391-16
239116f
APPLICATIONs INFOrmATION
Signal-to-Noise Ratio (SNR)
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC. Figure 5 shows
that the LTC2391-16 achieves a typical SNR of 94dB at a
250kHz sampling rate with a 20kHz input.
Total Harmonic Distortion (THD)
Totalharmonicdistortion(THD)istheratiooftheRMSsum
ofallharmonicsoftheinputsignaltothefundamentalitself.
The out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency (fSMPL/2).
THD is expressed as:
THD
V
V V
V
N
=
+
20
2
3
2
4
2
1
log
...
where V1 is the RMS amplitude of the fundamental fre-
quencyandV2throughVNaretheamplitudesofthesecond
through Nth harmonics.
POWER CONSIDERATIONS
The LTC2391-16 provides three sets of power supply
pins: the analog 5V power supply (AVP), the digital 5V
power supply (DVP) and the digital input/output interface
power supply (OVP). The flexible OVP supply allows the
LTC2391-16tocommunicatewithanydigitallogicoperating
between 1.8V and 5V, including 2.5V and 3.3V systems.
Power Supply Sequencing
The LTC2391-16 does not have any specific power sup-
ply sequencing requirements. Care should be taken to
observe the maximum voltage relationships described in
the Absolute Maximum Ratings section. The LTC2391-16
has a power-on reset (POR) circuit. With the POR, the
result of the first conversion is valid after power has
been applied to the ADC. The LTC2391-16 will reset itself
if the power supply voltage drops below 2.5V. Once the
supply voltage is brought back to its nominal value, the
POR will reinitialize the ADC and it will be ready to start
a new conversion.
Nap Mode
The LTC2391-16 can be put into the nap mode after a
conversion has been completed to reduce the power
consumption between conversions. In this mode some
of the circuitry on the device is turned off. Nap mode is
enabledbykeepingCNVSTlowbetweenconversions.When
the next conversion is requested, bring CNVST high and
hold for at least 250ns, then start the next conversion by
bringing CNVST low. See Figure 6.
Power Shutdown Mode
When PD is tied high, the LTC2391-16 enters power shut-
downandsubsequentrequestsforconversionareignored.
Before entering power shutdown, the digital output data
needstoberead.However,ifarequestforpowershutdown
(PD = high) occurs during a conversion, the conversion
will finish and then the device will power down. The data
Figure 6. Nap Mode Timing for the LTC2391-16
CNVST
BUSY
NAP
tCONV
tACQ
NAP MODE
239116 F06
t5
相關(guān)PDF資料
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LTC2391ILX-16#PBF SUCCESSIVE APPROXIMATION ADC, PQFP48
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