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參數(shù)資料
| 型號： | LTC2383CDE-16#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 7/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT 1CH 1MSPS 16-DFN |
| 標準包裝： | 2,500 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 16.25mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-WFDFN 裸露焊盤 |
| 供應商設備封裝： | 16-DFN（4x3） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
| 配用： | DC1571A-A-ND - BOARD SAR ADC LTC2383-16 |
LTC2383-16
15
238316f
Internal Conversion Clock
The LTC2383-16 has an internal clock that is trimmed to
achieve a maximum conversion time of 730ns. With a min-
imum acquisition time of 250ns, throughput performance
of 1Msps is guaranteed without any external
adjustments.
Auto Power-Down
The LTC2383-16 automatically powers down after a
conversion has been completed as long as CNV remains
high. During power down, the data from the last conversion
can be clocked out. To minimize power dissipation during
power down, disable SDO and turn off SCK. To power up
the part, bring CNV low at least 200ns (tCONVL) before the
initiation of the next conversion. The auto power-down
feature will reduce the power dissipation of the LTC2383-
16 as the sampling frequency is reduced. Since the time
required to power up the part does not change at lower
sample rates, the LTC2383-16 can remain powered-down
for a larger fraction of the conversion cycle (tCYC), thereby
reducing the average power dissipation which scales
linearly with sampling rate as shown in Figure 11.
APPLICATIONS INFORMATION
DIGITAL INTERFACE
The LTC2383-16 has a serial digital interface. The flexible
OVDD supply allows the LTC2383-16 to communicate with
any digital logic operating between 1.8V and 5V, including
2.5V and 3.3V systems.
The serial output data is clocked out on the SDO pin
when an external clock is applied to the SCK pin if SDO
is enabled. Clocking out the data after the conversion will
yield the best performance. With a shift clock frequency
of at least 60MHz, a 1Msps throughput is still achieved.
The serial output data changes state on the rising edge
of SCK and can be captured on the falling edge or next
rising edge of SCK. D15 remains valid till the first rising
edge of SCK.
The serial interface on the LTC2383-16 is simple and
straightforward to use. The following sections describe the
operation of the LTC2383-16. Several modes are provided
depending on whether a single or multiple ADCs share the
SPI bus or are daisy-chained.
SAMPLING RATE (kHz)
0
200
400
600
800
1000
0
POWER
SUPPL
Y
CURRENT
(mA)
5
4
2
1
3
6
238316 F11
Figure 11. Power Supply Current of the LTC2383-16
Versus Sampling Rate
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