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參數(shù)資料
| 型號： | LTC2380HMS-16#TRPBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | SUCCESSIVE APPROXIMATION ADC, PDSO16 |
| 封裝： | LEAD FREE, PLASTIC, MSOP-16 |
| 文件頁數(shù)： | 23/24頁 |
| 文件大小： | 545K |
| 代理商： | LTC2380HMS-16#TRPBF |
LTC2380-16
8
238016f
CHAIN (Pin 1): Chain Mode Selector Pin. When low, the
LTC2380-16 operates in Normal Mode and the RDL/SDI
input pin functions to enable or disable SDO. When high,
the LTC2380-16 operates in Chain Mode and the RDL/
SDI pin functions as SDI, the daisychain serial data input.
Logic levels are determined by 0VDD.
VDD (Pin 2): 2.5V Power Supply. The range of VDD is
2.375V to 2.625V. Bypass VDDtoGNDwitha10Fceramic
capacitor.
GND (Pins 3, 6, 10 and 16): Ground.
IN+, IN– (Pins 4, 5): Positive and Negative Differential
Analog Inputs.
REF (Pin 7): Reference Input. The range of REF is 2.5V
to 5.1V. This pin is referred to the GND pin and should be
decoupled closely to the pin with a 47F ceramic capacitor
(X5R, 0805 size).
REF/DGC(Pin8):WhentiedtoREF,digitalgaincompression
isdisabledandtheLTC2380-16definesfull-scaleaccording
to the ±VREF analog input range. When tied to GND, digital
gain compression is enabled and the LTC2380-16 defines
full-scale with inputs that swing between 10% and 90%
of the ±VREF analog input range.
CNV (Pin 9): Convert Input. A rising edge on this input
powers up the part and initiates a new conversion. Logic
levels are determined by 0VDD.
BUSY (Pin 11): BUSY indicator. Goes high at the start of
a new conversion and returns low when the conversion
has finished. Logic levels are determined by 0VDD.
RDL/SDI (Pin 12): When CHAIN is low, the part is in Nor-
mal Mode and the pin is treated as a bus enabling input.
When CHAIN is high, the part is in chain mode and the
pin is treated as a serial data input pin where data from
another ADC in the daisychain is input. Logic levels are
determined by 0VDD.
SCK(Pin13):SerialDataClockInput.WhenSDOisenabled,
the conversion result or daisychain data from another ADC
is shifted out on the rising edges of this clock MSB first.
Logic levels are determined by 0VDD.
SDO (Pin 14): Serial Data Output. The conversion result or
daisychain data is output on this pin on each rising edge
of SCK MSB first. The output data is in 2’s complement
format. Logic levels are determined by 0VDD.
OVDD (Pin 15): I/O Interface Digital Power. The range of
OVDD is 1.71V to 5.25V. This supply is nominally set to
the same supply as the host interface (1.8V, 2.5V, 3.3V,
or 5V). Bypass OVDD to GND with a 0.1F capacitor.
GND (Exposed Pad Pin 17 – DFN Package Only): Ground.
Exposedpadmustbesoldereddirectlytothegroundplane.
FuncTional block DiagraM
pin FuncTions
REF = 5V
LTC2380-16
IN+
VDD = 2.5V
OVDD = 1.8V to 5V
IN–
CHAIN
CNV
GND
BUSY
REF/DGC
SDO
SCK
RDL/SDI
CONTROL LOGIC
16-BIT SAMPLING ADC
SPI
PORT
+
–
238016 BD01
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