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參數(shù)資料
| 型號： | LTC2380CMS-16#TRPBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | SUCCESSIVE APPROXIMATION ADC, PDSO16 |
| 封裝： | LEAD FREE, PLASTIC, MSOP-16 |
| 文件頁數(shù)： | 20/24頁 |
| 文件大?。?/td> | 545K |
| 代理商： | LTC2380CMS-16#TRPBF |
LTC2380-16
5
238016f
aDc TiMing characTerisTics The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
tSCKL
SCK Low Time
l
4
ns
tSSDISCK
SDI Setup Time From SCK ↑
(Note 11)
l
4
ns
tHSDISCK
SDI Hold Time From SCK ↑
(Note 11)
l
1
ns
tSCKCH
SCK Period in Chain Mode
tSCKCH = tSSDISCK + tDSDO (Note 11)
l
13.5
ns
tDSDO
SDO Data Valid Delay from SCK ↑
CL = 20pF (Note 11)
l
9.5
ns
tHSDO
SDO Data Remains Valid Delay from SCK ↑
CL = 20pF (Note 10)
l
1
ns
tDSDOBUSYL SDO Data Valid Delay from BUSY ↓
CL = 20pF (Note 10)
l
5
ns
tEN
Bus Enable Time After RDL ↓
(Note 11)
l
16
ns
tDIS
Bus Relinquish Time After RDL ↑
(Note 11)
l
13
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may effect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground.
Note 3: When these pin voltages are taken below ground or above REFor
OVDD, they will be clamped by internal diodes. This product can handle
input currents up to 100mA below ground or above REF or OVDD without
latch-up.
Note 4: VDD = 2.5V, OVDD = 2.5V, REF = 5V, VCM = 2.5V, fSMPL = 2MHz,
REF/DGC = VREF.
Note 5: Recommended operating conditions.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: Bipolar zero-scale error is the offset voltage measured from
–0.5LSB when the output code flickers between 0000 0000 0000 0000 and
1111 1111 1111 1111. Full-scale bipolar error is the worst-case of –FS
or +FS untrimmed deviation from ideal first and last code transitions and
includes the effect of offset error.
Note 8: All specifications in dB are referred to a full-scale ±5V input with a
5V reference voltage.
Note 9: fSMPL = 2MHz, IREF varies proportionately with sample rate.
Note 10: Guaranteed by design, not subject to test.
Note 11: Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V
and OVDD = 5.25V.
Note 12: tSCK of 10ns maximum allows a shift clock frequency up to
100MHz for rising capture.
0.8*OVDD
0.2*OVDD
50%
238016 F01
0.2*OVDD
0.8*OVDD
0.2*OVDD
0.8*OVDD
tDELAY
tWIDTH
tDELAY
Figure 1. Voltage Levels for Timing Specifications
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