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參數(shù)資料
| 型號(hào)： | LTC2379IMS-18#TRPBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類(lèi)： | ADC |
| 英文描述： | 1-CH 18-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO16 |
| 封裝： | LEAD FREE, PLASTIC, MSOP-16 |
| 文件頁(yè)數(shù)： | 7/24頁(yè) |
| 文件大?。?/td> | 2848K |
| 代理商： | LTC2379IMS-18#TRPBF |
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LTC2379-18
15
237918f
reinitialize the ADC. No conversions should be initiated
until 20s after a POR event to ensure the reinitialization
period has ended. Any conversions initiated before this
time will produce invalid results.
TIMING AND CONTROL
CNV Timing
The LTC2379-18 conversion is controlled by CNV. A ris-
ing edge on CNV will start a conversion and power up the
LTC2379-18.Onceaconversionhasbeeninitiated,itcannot
berestarteduntiltheconversioniscomplete.Foroptimum
performance, CNV should be driven by a clean low jitter
signal. Converter status is indicated by the BUSY output
which remains high while the conversion is in progress.
To ensure that no errors occur in the digitized results, any
additional transitions on CNV should occur within 40ns
from the start of the conversion or after the conversion
has been completed. Once the conversion has completed,
the LTC2379-18 powers down and begins acquiring the
input signal.
Internal Conversion Clock
The LTC2379-18 has an internal clock that is trimmed to
achieveamaximumconversiontimeof412ns.Withamin-
imum acquisition time of 200ns, throughput performance
of1.6Mspsisguaranteedwithoutanyexternaladjustments.
Auto Power-Down
The LTC2379-18 automatically powers down after a con-
version has been completed and powers up once a new
conversion is initiated on the rising edge of CNV. During
power down, data from the last conversion can be clocked
out. To minimize power dissipation during power down,
disableSDOandturnoffSCK.Theautopower-downfeature
will reduce the power dissipation of the LTC2379-18 as
the sampling frequency is reduced. Since power is con-
sumed only during a conversion, the LTC2379-18 remains
APPLICATIONS INFORMATION
powered-down for a larger fraction of the conversion cycle
(tCYC) at lower sample rates, thereby reducing the average
power dissipation which scales with the sampling rate as
shown in Figure 12.
DIGITAL INTERFACE
The LTC2379-18 has a serial digital interface. The flexible
OVDD supply allows the LTC2379-18 to communicate with
any digital logic operating between 1.8V and 5V, including
2.5V and 3.3V systems.
The serial output data is clocked out on the SDO pin when
anexternalclockisappliedtotheSCKpinifSDOisenabled.
Clocking out the data after the conversion will yield the
best performance. With a shift clock frequency of at least
100MHz,a1.6Mspsthroughputisstillachieved.Theserial
output data changes state on the rising edge of SCK and
can be captured on the falling edge or next rising edge of
SCK. D17 remains valid till the first rising edge of SCK.
The serial interface on the LTC2379-18 is simple and
straightforwardtouse.Thefollowingsectionsdescribethe
operation of the LTC2379-18. Several modes are provided
depending on whether a single or multiple ADCs share the
SPI bus or are daisychained.
SAMPLING RATE (kHz)
0
200 400 600 800
1600
1400
1200
1000
0
POWER
SUPPL
YCURRENT
(mA)
5
4
2
1
3
8
7
6
237918 F12
IVDD
IREF
IOVDD
Figure 12. Power Supply Current of the LTC2379-18
Versus Sampling Rate
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| LTC2379IDE-18#PBF | 1-CH 18-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO16 |
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