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參數(shù)資料
| 型號： | LTC2366CTS8#TRMPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 7/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 3MSPS TSOT23-8 |
| 標準包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 3M |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 14.4mW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-8 薄型，TSOT-23-8 |
| 供應商設備封裝： | TSOT-23-8 |
| 包裝： | 標準包裝 |
| 輸入數(shù)目和類型： | 1 個單端，單極 |
| 產品目錄頁面： | 1347 (CN2011-ZH PDF) |
| 其它名稱： | LTC2366CTS8#TRMPBFDKR |
LTC2365/LTC2366
15
23656fb
For more information www.linear.com/LTC2365
Achieving 3Msps Sample Rate with LTC2366
CS going LOW places the sample-and-hold into hold
mode and starts a conversion. The LTC2365/LTC2366
require at least 14 SCK cycles to finish the conversion.
The conversion terminates after the 13th falling SCK edge,
which clocks out B0. The 14th falling SCK edge places the
sample-and-hold back into sample mode.
Ignoring the last two trailing zeros, the user can bring CS
HIGH after the 14th falling SCK edge. The user can also
keep the last two trailing zeros by bringing CS HIGH right
after the 16th falling SCK. In both cases, a sample rate of
3Msps can be achieved by using a 48MHz SCK clock on
the LTC2366, where tTHROUGHPUT is 333ns.
Serial Data Output (SDO)
The SDO output remains in the high impedance state while
CS is HIGH. The falling edge of CS starts the conversion
and enables SDO. The A/D conversion result is shifted out
on the SDO pin as a serial data stream with the MSB first.
The data stream consists of two leading zeros followed
by 12 bits of conversion data and two trailing zeros. The
SDO output returns to the high impedance state at the
16th falling edge of SCK or sooner by bringing CS HIGH
before the 16th falling edge of SCK.
The output swing on the SDO pin is controlled by the VDD
pin voltage in the S6 package and by the OVDD pin voltage
in the TS8 package.
Figure 11. LTC2365/LTC2366 Serial Interface Timing Diagram for 14 SCK Cycles
Figure 12. LTC2365/LTC2366 Serial Interface Timing Diagram for 16 SCK Cycles
applications inForMation
1
SCK
SDO
t2
t3
t4
t7
t9
t5
Z
ZERO
B11
B10
B9
B1
B0
2
3
4
(MSB)
Hi-Z STATE
5
13
14
t6
tACQ
tQUIET
tTHROUGHPUT
tCONV
CS
t1
23656 F11
1
SCK
SDO
t2
t3
t4
t7
t8 OR t9
t5
2
3
4
(MSB)
Hi-Z STATE
5
13
14
15
16
t6
tACQ
tQUIET
tTHROUGHPUT
tCONV
CS
t1
23656 F12
Z
ZERO
B11
B10
B9
B1
B0
ZERO
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