參數(shù)資料
型號: LTC2355CMSE-12#TR
廠商: LINEAR TECHNOLOGY CORP
元件分類: ADC
英文描述: 1-CH 12-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PDSO10
封裝: PLASTIC, MSOP-10
文件頁數(shù): 1/16頁
文件大小: 220K
代理商: LTC2355CMSE-12#TR
1
LTC2355-12/LTC2355-14
2355f
APPLICATIO S
U
FEATURES
DESCRIPTIO
U
BLOCK DIAGRA
W
Serial 12-Bit/14-Bit, 3.5Msps
Sampling ADCs with Shutdown
3.5Msps Conversion Rate
74.2dB SINAD at 14-Bits, 71.1dB SINAD at 12-Bits
Low Power Dissipation: 18mW
3.3V Single Supply Operation
2.5V Internal Bandgap Reference can be Overdriven
3-Wire SPI-Compatible Serial Interface
Sleep (13
W) Shutdown Mode
Nap (4mW) Shutdown Mode
80dB Common Mode Rejection
0V to 2.5V Unipolar Input Range
Tiny 10-Lead MSOP Package
Communications
Data Acquisition Systems
Uninterrupted Power Supplies
Multiphase Motor Control
Multiplexed Data Acquisition
RFID
THD, 2nd, 3rd and SFDR
vs Input Frequency
The LTC
2355-12/LTC2355-14 are 12-bit/14-bit, 3.5Msps
serial ADCs with differential inputs. The devices draw only
5.5mA from a single 3.3V supply and come in a tiny 10-lead
MSOP package. A Sleep shutdown feature further reduces
power consumption to 13
W. The combination of speed,
low power and tiny package makes the LTC2355-12/
LTC2355-14 suitable for high speed, portable applications.
The 80dB common mode rejection allows users to elimi-
nate ground loops and common mode noise by measuring
signals differentially from the source.
The devices convert 0V to 2.5V unipolar inputs differentially.
The absolute voltage swing for AIN+ and AIN– extends from
ground to the supply voltage.
The serial interface sends out the conversion results during
the 16 clock cycles following a CONV rising edge for
compatibility with standard serial interfaces. If two addi-
tional clock cycles for acquisition time are allowed after the
data stream in between conversions, the full sampling rate
of 3.5Msps can be achieved with a 63MHz clock.
+
1
2
7
3
4
S & H
GND
EXPOSED PAD
LTC2355-14
VREF
10
F
AIN
AIN
+
14-BIT ADC
3.3V
10
F
14
14-BIT
LATCH
8
10
9
THREE-
STATE
SERIAL
OUTPUT
PORT
2.5V
REFERENCE
TIMING
LOGIC
VDD
SDO
CONV
SCK
2355 TA01
5
6
11
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
FREQUENCY (MHz)
0.1
–80
THD,
2nd,
3rd
(dB) –74
–68
–62
–56
1
10
100
2355 G02
–86
–92
–98
–104
–110
–50
THD
2nd
3rd
相關PDF資料
PDF描述
LTC2355IMSE-12#TR 1-CH 12-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PDSO10
LTC2355IMSE-14#TR 1-CH 14-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PDSO10
LTC2355CMSE-14#TR 1-CH 14-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PDSO10
LTC2356CMSE-12#TR 1-CH 12-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PDSO10
LTC2356IMSE-12#TR 1-CH 12-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PDSO10
相關代理商/技術參數(shù)
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