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參數(shù)資料
| 型號： | LTC2297IUP#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 13/28頁 |
| 文件大小： | 0K |
| 描述： | IC ADC DUAL 14BIT 40MSPS 64QFN |
| 標準包裝： | 2,000 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 40M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 285mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 64-QFN（9x9） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個單端，雙極; 2 個差分, 雙極 |
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LTC2298/LTC2297/LTC2296
20
229876fa
CLK
5pF-30pF
ETC1-1T
0.1
F
VCM
FERRITE
BEAD
DIFFERENTIAL
CLOCK
INPUT
229876 F13
LTC2298
LTC2297
LTC2296
CLK
100
0.1
F
4.7
F
FERRITE
BEAD
CLEAN
SUPPLY
IF LVDS USE FIN1002 OR FIN1018.
FOR PECL, USE AZ1000ELT21 OR SIMILAR
229876 F12
LTC2298
LTC2297
LTC2296
APPLICATIO S I FOR ATIO
WU
UU
The noise performance of the LTC2298/LTC2297/LTC2296
can depend on the clock signal quality as much as on the
analog input. Any noise present on the clock signal will
result in additional aperture jitter that will be RMS summed
with the inherent ADC aperture jitter.
In applications where jitter is critical, such as when digitiz-
ing high input frequencies, use as large an amplitude as
possible. Also, if the ADC is clocked with a sinusoidal
signal, filter the CLK signal to reduce wideband noise and
distortion products generated by the source.
It is recommended that CLKA and CLKB are shorted
together and driven by the same clock source. If a small
time delay is desired between when the two channels
sample the analog inputs, CLKA and CLKB can be driven
by two different signals. If this delay exceeds 1ns, the
performance of the part may degrade. CLKA and CLKB
should not be driven by asynchronous signals.
Figures 12 and 13 show alternatives for converting a
differential clock to the single-ended CLK input. The use of
a transformer provides no incremental contribution to
phase noise. The LVDS or PECL to CMOS translators
provide little degradation below 70MHz, but at 140MHz
will degrade the SNR compared to the transformer solu-
tion. The nature of the received signals also has a large
bearing on how much SNR degradation will be experi-
enced. For high crest factor signals such as WCDMA or
OFDM, where the nominal power level must be at least 6dB
to 8dB below full scale, the use of these translators will
have a lesser impact.
Figure 11. Sinusoidal Single-Ended CLK Drive
CLK
50
0.1
F
0.1
F
4.7
F
1k
FERRITE
BEAD
CLEAN
SUPPLY
SINUSOIDAL
CLOCK
INPUT
229876 F11
NC7SVU04
LTC2298
LTC2297
LTC2296
The transformer in the example may be terminated with
the appropriate termination for the signaling in use. The
use of a transformer with a 1:4 impedance ratio may be
desirable in cases where lower voltage differential signals
are considered. The center tap may be bypassed to
ground through a capacitor close to the ADC if the
differential signals originate on a different plane. The use
of a capacitor at the input may result in peaking, and
depending on transmission line length may require a 10
to 20
ohm series resistor to act as both a low pass filter
for high frequency noise that may be induced into the
clock line by neighboring digital signals, as well as a
damping mechanism for reflections.
Figure 13. LVDS or PECL CLK Drive Using a Transformer
Figure 12. CLK Drive Using an LVDS or PECL to CMOS Converter
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LTC2297UP | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Dual 14-Bit, 65/40/25Msps Low Power 3V ADCs |
| LTC2298 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Dual 14-Bit, 65/40/25Msps Low Power 3V ADCs |
| LTC2298CUP | 制造商:Linear Technology 功能描述:ADC Dual Pipelined 65Msps 14-bit Parallel 64-Pin QFN EP |
| LTC2298CUP#PBF | 功能描述:IC ADC DUAL 14BIT 65MSPS 64QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關文件:TSA1204 View All Specifications 標準包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應商設備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| LTC2298CUP#TR | 制造商:Linear Technology 功能描述:ADC Dual Pipelined 65Msps 14-bit Parallel 64-Pin QFN EP T/R |
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