參數(shù)資料
型號(hào)： LTC2296CUP
廠商： LINEAR TECHNOLOGY CORP
元件分類： ADC
英文描述： Dual 14-Bit, 65/40/25Msps Low Power 3V ADCs
中文描述： DUAL 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
封裝： 9 X 9 MM, PLASTIC, MO-220-WNJR, QFN-64
文件頁(yè)數(shù)： 21/28頁(yè)
文件大?。?/td> 706K
代理商： LTC2296CUP
LTC2298/LTC2297/LTC2296
21
229876f
between the digital outputs and sensitive input circuitry.
The output should be buffered with a device such as an
ALVCH16373 CMOS latch. For full speed operation the
capacitive load should be kept under 10pF.
Lower OV
DD
voltages will also help reduce interference
from the digital outputs.
Data Format
Using the MODE pin, the LTC2298/LTC2297/LTC2296
parallel digital output can be selected for offset binary or
2’s complement format. Note that MODE controls both
Channel A and Channel B. Connecting MODE to GND or
1/3V
DD
selects straight binary output format. Connecting
MODE to 2/3V
DD
or V
DD
selects 2’s complement output
format. An external resistor divider can be used to set the
1/3V
DD
or 2/3V
DD
logic values. Table 1 shows the logic
states for the MODE pin.
APPLICATIU
W
U
U
Overflow Bit
When OF outputs a logic high the converter is either
overranged or underranged.
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OV
DD
, should be tied
to the same power supply as for the logic being driven. For
example, if the converter is driving a DSP powered by a 1.8V
supply, then OV
DD
should be tied to that same 1.8V supply.
OV
DD
can be powered with any voltage from 500mV up to
3.6V. OGND can be powered with any voltage from GND up
to 1V and must be less than OV
DD
. The logic outputs will
swing between OGND and OV
DD
.
Output Enable
The outputs may be disabled with the output enable pin, OE.
OE high disables all data outputs including OF. The data ac-
cess and bus relinquish times are too slow to allow the
outputs to be enabled and disabled during full speed op-
eration. The output Hi-Z state is intended for use during long
periods of inactivity. Channels A and B have independent
output enable pins (OEA, OEB).
Table 1. MODE Pin Function
Clock Duty
Cycle Stabilizer
Off
On
On
Off
MODE Pin
0
1/3V
DD
2/3V
DD
V
DD
Output Format
Straight Binary
Straight Binary
2’s Complement
2’s Complement
Figure 12. Digital Output Buffer
229876 F12
OV
DD
V
DD
V
DD
0.1
μ
F
43
TYPICAL
DATA
OUTPUT
OGND
OV
DD
0.5V
TO V
DD
PREDRIVER
LOGIC
DATA
FROM
LATCH
OE
LTC2298/LTC2297/LTC2296
相關(guān)PDF資料
PDF描述
LTC2296IUP Dual 14-Bit, 65/40/25Msps Low Power 3V ADCs
LTC2296UP Dual 14-Bit, 65/40/25Msps Low Power 3V ADCs
LTC2297CUP Dual 14-Bit, 65/40/25Msps Low Power 3V ADCs
LTC2297IUP Dual 14-Bit, 65/40/25Msps Low Power 3V ADCs
LTC2297UP Dual 14-Bit, 65/40/25Msps Low Power 3V ADCs
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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LTC2296IUP 制造商:LINER 制造商全稱:Linear Technology 功能描述:Dual 14-Bit, 65/40/25Msps Low Power 3V ADCs
LTC2296IUP#PBF 功能描述:IC ADC DUAL 14BIT 25MSPS 64QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個(gè)單端，單極；2 個(gè)差分，單極 產(chǎn)品目錄頁(yè)面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6
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