參數(shù)資料
型號： LTC2292IUP
廠商： LINEAR TECHNOLOGY CORP
元件分類： ADC
英文描述： Dual 12-Bit, 65/40/25Msps Low Power 3V ADCs
中文描述： DUAL 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
封裝： 9 X 9 MM, PLASTIC, MO-220-WNJR, QFN-64
文件頁數(shù)： 21/28頁
文件大小： 1020K
代理商： LTC2292IUP
LTC2293/LTC2292/LTC2291
21
229321f
between the digital outputs and sensitive input circuitry.
The output should be buffered with a device such as an
ALVCH16373 CMOS latch. For full speed operation the
capacitive load should be kept under 10pF.
Lower OV
DD
voltages will also help reduce interference
from the digital outputs.
Data Format
Using the MODE pin, the LTC2293/LTC2292/LTC2291
parallel digital output can be selected for offset binary or
2’s complement format. Note that MODE controls both
Channel A and Channel B. Connecting MODE to GND or
1/3V
DD
selects straight binary output format. Connecting
MODE to 2/3V
DD
or V
DD
selects 2’s complement output
format. An external resistor divider can be used to set the
1/3V
DD
or 2/3V
DD
logic values. Table 1 shows the logic
states for the MODE pin.
APPLICATIU
W
U
U
Overflow Bit
When OF outputs a logic high the converter is either
overranged or underranged.
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OV
DD
, should be tied
to the same power supply as for the logic being driven. For
example, if the converter is driving a DSP powered by a 1.8V
supply, then OV
DD
should be tied to that same 1.8V supply.
OV
DD
can be powered with any voltage from 500mV up to
3.6V. OGND can be powered with any voltage from GND up
to 1V and must be less than OV
DD
. The logic outputs will
swing between OGND and OV
DD
.
Output Enable
The outputs may be disabled with the output enable pin, OE.
OE high disables all data outputs including OF. The data ac-
cess and bus relinquish times are too slow to allow the
outputs to be enabled and disabled during full speed op-
eration. The output Hi-Z state is intended for use during long
periods of inactivity. Channels A and B have independent
output enable pins (OEA, OEB).
Table 1. MODE Pin Function
Clock Duty
Cycle Stabilizer
Off
On
On
Off
MODE Pin
0
1/3V
DD
2/3V
DD
V
DD
Output Format
Straight Binary
Straight Binary
2’s Complement
2’s Complement
Figure 12. Digital Output Buffer
229321 F12
OV
DD
V
DD
V
DD
0.1
μ
F
43
TYPICAL
DATA
OUTPUT
OGND
OV
DD
0.5V
TO V
DD
PREDRIVER
LOGIC
DATA
FROM
LATCH
OE
LTC2293/LTC2292/LTC2291
相關(guān)PDF資料
PDF描述
LTC2292UP Dual 12-Bit, 65/40/25Msps Low Power 3V ADCs
LTC2293CUP Dual 12-Bit, 65/40/25Msps Low Power 3V ADCs
LTC2293IUP Dual 12-Bit, 65/40/25Msps Low Power 3V ADCs
LTC2293UP Dual 12-Bit, 65/40/25Msps Low Power 3V ADCs
LTC2291CUP Dual 12-Bit, 65/40/25Msps Low Power 3V ADCs
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LTC2292IUP#PBF 功能描述:IC ADC DUAL 12BIT 40MSPS 64QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極
LTC2292IUP#TRPBF 功能描述:IC ADC DUAL 12BIT 40MSPS 64QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個單端，單極；1 個單端，雙極
LTC2292UP 制造商:LINER 制造商全稱:Linear Technology 功能描述:Dual 12-Bit, 65/40/25Msps Low Power 3V ADCs
LTC2293 制造商:LINER 制造商全稱:Linear Technology 功能描述:14-Bit, 125/105Msps Low Power 3V ADCs
LTC2293CUP 制造商:LINER 制造商全稱:Linear Technology 功能描述:Dual 12-Bit, 65/40/25Msps Low Power 3V ADCs
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