參數(shù)資料
型號(hào): LTC2292CUP#TRPBF
廠商: Linear Technology
文件頁(yè)數(shù): 1/28頁(yè)
文件大?。?/td> 0K
描述: IC ADC DUAL 12BIT 40MSPS 64QFN
標(biāo)準(zhǔn)包裝: 2,000
位數(shù): 12
采樣率(每秒): 40M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 285mW
電壓電源: 單電源
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 64-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 64-QFN(9x9)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個(gè)單端,雙極; 2 個(gè)差分, 雙極
LTC2293/LTC2292/LTC2291
1
229321fa
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
INPUT FREQUENCY (MHz)
0
SNR
(dBFS)
70
71
200
229321 TA02
69
68
50
100
150
72
FEATURES
DESCRIPTIO
U
APPLICATIO S
U
TYPICAL APPLICATIO
U
Integrated Dual 12-Bit ADCs
Sample Rate: 65Msps/40Msps/25Msps
Single 3V Supply (2.7V to 3.4V)
Low Power: 400mW/235mW/150mW
71.3dB SNR
90dB SFDR
110dB Channel Isolation at 100MHz
Multiplexed or Separate Data Bus
Flexible Input: 1VP-P to 2VP-P Range
575MHz Full Power Bandwidth S/H
Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
Pin Compatible Family
105Msps: LTC2282 (12-Bit), LTC2284 (14-Bit)
80Msps: LTC2294 (12-Bit), LTC2299 (14-Bit)
65Msps: LTC2293 (12-Bit), LTC2298 (14-Bit)
40Msps: LTC2292 (12-Bit), LTC2297 (14-Bit)
25Msps: LTC2291 (12-Bit), LTC2296 (14-Bit)
10Msps: LTC2290 (12-Bit), LTC2295 (14-Bit)
64-Pin (9mm
× 9mm) QFN Package
Dual 12-Bit, 65/40/25Msps
Low Power 3V ADCs
The LTC
2293/LTC2292/LTC2291 are 12-bit 65Msps/
40Msps/25Msps, low power dual 3V A/D converters de-
signed for digitizing high frequency, wide dynamic range
signals. The LTC2293/LTC2292/LTC2291 are perfect for
demanding imaging and communications applications
with AC performance that includes 71.3dB SNR and 90dB
SFDR for signals at the Nyquist frequency.
DC specs include
±0.3LSB INL (typ), ±0.15LSB DNL (typ)
and no missing codes over temperature. The transition
noise is a low 0.25LSBRMS.
A single 3V supply allows low power operation. A separate
output supply allows the outputs to drive 0.5V to 3.6V
logic. An optional multiplexer allows both channels to
share a digital output bus.
A single-ended CLK input controls converter operation. An
optional clock duty cycle stabilizer allows high perfor-
mance at full speed for a wide range of clock duty cycles.
LTC2293: SNR vs Input Frequency,
–1dB, 2V Range, 65Msps
+
INPUT
S/H
ANALOG
INPUT A
ANALOG
INPUT B
CLK A
CLK B
12-BIT
PIPELINED
ADC CORE
CLOCK/DUTY CYCLE
CONTROL
OUTPUT
DRIVERS
OVDD
OGND
MUX
D11A
D0A
OVDD
OGND
229321 TA01
D11B
D0B
+
OUTPUT
DRIVERS
INPUT
S/H
12-BIT
PIPELINED
ADC CORE
CLOCK/DUTY CYCLE
CONTROL
Wireless and Wired Broadband Communication
Imaging Systems
Spectral Analysis
Portable Instrumentation
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參數(shù)描述
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