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參數(shù)資料
| 型號(hào)： | LTC2291IUP |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | Dual 12-Bit, 65/40/25Msps Low Power 3V ADCs |
| 中文描述： | DUAL 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| 封裝： | 9 X 9 MM, PLASTIC, MO-220-WNJR, QFN-64 |
| 文件頁(yè)數(shù)： | 12/28頁(yè) |
| 文件大小： | 1020K |
| 代理商： | LTC2291IUP |
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LTC2293/LTC2292/LTC2291
12
229321f
MUX (Pin 21):
Digital Output Multiplexer Control. If MUX
is High, Channel A comes out on DA0-DA13, OFA; Channel B
comes out on DB0-DB13, OFB. If MUX is Low, the output
busses are swapped and Channel A comes out on DB0-
DB13, OFB; Channel B comes out on DA0-DA13, OFA. To
multiplex both channels onto a single output bus, connect
MUX, CLKA and CLKB together.
SHDNB (Pin 22):
Channel B Shutdown Mode Selection
Pin. Connecting SHDNB to GND and OEB to GND results
in normal operation with the outputs enabled. Connecting
SHDNB to GND and OEB to V
DD
results in normal opera-
tion with the outputs at high impedance. Connecting
SHDNB to V
DD
and OEB to GND results in nap mode with
the outputs at high impedance. Connecting SHDNB to V
DD
and OEB to V
DD
results in sleep mode with the outputs at
high impedance.
OEB (Pin 23):
Channel B Output Enable Pin. Refer to
SHDNB pin function.
NC (Pins 24, 25, 41, 42):
Do Not Connect These Pins.
DB0 – DB11 (Pins 26 to 30, 33 to 39):
Channel B Digital
Outputs. DB11 is the MSB.
OGND (Pins 31, 50):
Output Driver Ground.
OV
DD
(Pins 32, 49):
Positive Supply for the Output Driv-
ers. Bypass to ground with 0.1
μ
F ceramic chip capacitor.
OFB (Pin 40):
Channel B Overflow/Underflow Output.
High when an overflow or underflow has occurred.
DA0 – DA11 (Pins 43 to 48, 51 to 56):
Channel A Digital
Outputs. DA11 is the MSB.
OFA (Pin 57):
Channel A Overflow/Underflow Output.
High when an overflow or underflow has occurred.
OEA (Pin 58):
Channel A Output Enable Pin. Refer to
SHDNA pin function.
SHDNA (Pin 59):
Channel A Shutdown Mode Selection
Pin. Connecting SHDNA to GND and OEA to GND results
in normal operation with the outputs enabled. Connecting
SHDNA to GND and OEA to V
DD
results in normal opera-
tion with the outputs at high impedance. Connecting
SHDNA to V
DD
and OEA to GND results in nap mode with
the outputs at high impedance. Connecting SHDNA to V
DD
and OEA to V
DD
results in sleep mode with the outputs at
high impedance.
MODE (Pin 60):
Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Note that MODE controls both
channels. Connecting MODE to GND selects straight bi-
nary output format and turns the clock duty cycle stabilizer
off. 1/3 V
DD
selects straight binary output format and turns
the clock duty cycle stabilizer on. 2/3 V
DD
selects 2’s
complement output format and turns the clock duty cycle
stabilizer on. V
DD
selects 2’s complement output format
and turns the clock duty cycle stabilizer off.
V
CMA
(Pin 61):
Channel A 1.5V Output and Input Common
Mode Bias. Bypass to ground with 2.2
μ
F ceramic chip
capacitor. Do not connect to V
CMB
.
SENSEA (Pin 62):
Channel A Reference Programming Pin.
Connecting SENSEA to V
CMA
selects the internal reference
and a
±
0.5V input range. V
DD
selects the internal reference
and a
±
1V input range. An external reference greater than
0.5V and less than 1V applied to SENSEA selects an input
range of
±
V
SENSEA
.
±
1V is the largest valid input range.
GND (Exposed Pad) (Pin 65):
ADC Power Ground. The
Exposed Pad on the bottom of the package needs to be
soldered to ground.
PIU
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相關(guān)代理商/技術(shù)參數(shù) |
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| LTC2291IUP#PBF | 功能描述:IC ADC DUAL 12BIT 25MSPS 64QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個(gè)單端，單極；2 個(gè)差分，單極 產(chǎn)品目錄頁(yè)面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| LTC2291IUP#TRPBF | 功能描述:IC ADC DUAL 12BIT 25MSPS 64QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個(gè)單端，單極；1 個(gè)單端，雙極 |
| LTC2291UP | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Dual 12-Bit, 65/40/25Msps Low Power 3V ADCs |
| LTC2292 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Dual 12-Bit, 65/40/25Msps Low Power 3V ADCs |
| LTC2292CUP | 制造商:Linear Technology 功能描述:ADC Dual Pipelined 40Msps 12-bit Parallel 64-Pin QFN EP |
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