參數(shù)資料
型號(hào)： LTC2291
廠商： Linear Technology Corporation
英文描述： Dual 12-Bit, 65/40/25Msps Low Power 3V ADCs
中文描述： 雙12位，65/40/25Msps低功耗3V的模數(shù)轉(zhuǎn)換器
文件頁(yè)數(shù)： 17/28頁(yè)
文件大小： 1020K
代理商： LTC2291
LTC2293/LTC2292/LTC2291
17
229321f
capacitors to acquire a new sample. Since the sampling
capacitors still hold the previous sample, a charging glitch
proportional to the change in voltage between samples will
be seen at this time. If the change between the last sample
and the new sample is small, the charging glitch seen at
the input will be small. If the input change is large, such as
the change seen with input frequencies near Nyquist, then
a larger charging glitch will be seen.
Single-Ended Input
For cost sensitive applications, the analog inputs can be
driven single-ended. With a single-ended input the har-
monic distortion and INL will degrade, but the SNR and
DNL will remain unchanged. For a single-ended input, A
IN+
should be driven with the input signal and A
IN–
should be
connected to 1.5V or V
CM
.
Common Mode Bias
For optimal performance the analog inputs should be
driven differentially. Each input should swing
±
0.5V for
the 2V range or
±
0.25V for the 1V range, around a
common mode voltage of 1.5V. The V
CM
output pin may
be used to provide the common mode bias level. V
CM
can
be tied directly to the center tap of a transformer to set the
DC input level or as a reference level to an op amp
differential driver circuit. The V
CM
pin must be bypassed to
ground close to the ADC with a 2.2
μ
F or greater capacitor.
Input Drive Impedance
As with all high performance, high speed ADCs, the
dynamic performance of the LTC2293/LTC2292/LTC2291
can be influenced by the input drive circuitry, particularly
the second and third harmonics. Source impedance and
reactance can influence SFDR. At the falling edge of CLK,
the sample-and-hold circuit will connect the 4pF sampling
capacitor to the input pin and start the sampling period.
The sampling period ends when CLK rises, holding the
sampled input on the sampling capacitor. Ideally the input
circuitry should be fast enough to fully charge
the sampling capacitor during the sampling period
1/(2F
ENCODE
); however, this is not always possible and the
incomplete settling may degrade the SFDR. The sampling
APPLICATIOU
W
U
U
glitch has been designed to be as linear as possible to
minimize the effects of incomplete settling.
For the best performance, it is recommended to have a
source impedance of 100
or less for each input. The
source impedance should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
Input Drive Circuits
Figure 3 shows the LTC2293/LTC2292/LTC2291 being
driven by an RF transformer with a center tapped second-
ary. The secondary center tap is DC biased with V
CM
,
setting the ADC input signal at its optimum DC level.
Terminating on the transformer secondary is desirable, as
this provides a common mode path for charging glitches
caused by the sample and hold. Figure 3 shows a 1:1 turns
ratio transformer. Other turns ratios can be used if the
source impedance seen by the ADC does not exceed 100
for each ADC input. A disadvantage of using a transformer
is the loss of low frequency response. Most small RF
transformers have poor performance at frequencies be-
low 1MHz.
Figure 3. Single-Ended to Differential Conversion
Using a Transformer
25
25
25
25
0.1
μ
F
A
IN+
A
IN–
12pF
2.2
μ
F
V
CM
LTC2293
LTC2292
LTC2291
ANALOG
INPUT
0.1
μ
F
T1
1:1
T1 = MA/COM ETC1-1T
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
229321 F03
Figure 4 demonstrates the use of a differential amplifier to
convert a single ended input signal into a differential input
signal. The advantage of this method is that it provides low
frequency input response; however, the limited gain band-
width of most op amps will limit the SFDR at high input
frequencies.
相關(guān)PDF資料
PDF描述
LTC2291UP Dual 12-Bit, 65/40/25Msps Low Power 3V ADCs
LTC2292CUP Dual 12-Bit, 65/40/25Msps Low Power 3V ADCs
LTC2292IUP Dual 12-Bit, 65/40/25Msps Low Power 3V ADCs
LTC2292UP Dual 12-Bit, 65/40/25Msps Low Power 3V ADCs
LTC2293CUP Dual 12-Bit, 65/40/25Msps Low Power 3V ADCs
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LTC2291CUP 制造商:Linear Technology 功能描述:ADC Dual Pipelined 25Msps 12-bit Parallel 64-Pin QFN EP
LTC2291CUP#PBF 功能描述:IC ADC DUAL 12BIT 25MSPS 64QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個(gè)單端，單極；2 個(gè)差分，單極 產(chǎn)品目錄頁(yè)面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6
LTC2291CUP#TRPBF 功能描述:IC ADC DUAL 12BIT 25MSPS 64QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個(gè)單端，單極；1 個(gè)單端，雙極
LTC2291CUPPBF 制造商:Linear Technology 功能描述:ADC Dual 25Msps 12-Bit Parallel QFN64EP
LTC2291IUP 制造商:Linear Technology 功能描述:MS-ADC/High Speed, Dual 12-bit, 25Msps Low Power ADC
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