參數(shù)資料
型號(hào)： LTC2285IUP#PBF
廠商： Linear Technology
文件頁(yè)數(shù)： 4/24頁(yè)
文件大?。?/td> 0K
描述： IC ADC DUAL 14BIT 125MSPS 64QFN
標(biāo)準(zhǔn)包裝： 40
位數(shù)： 14
采樣率（每秒）： 125M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 915mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 64-QFN（9x9）
包裝： 管件
輸入數(shù)目和類型： 2 個(gè)單端，雙極; 2 個(gè)差分, 雙極
LTC2285
12
2285fb
APPLICATIONS INFORMATION
with slightly worse harmonic distortion. The CLK input is
single-ended. The LTC2285 has two phases of operation,
determined by the state of the CLK input pin.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage residue amplier.
In operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplied and
output by the residue amplier. Successive stages operate
out of phase so that when the odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
When CLK is low, the analog input is sampled differentially
directly onto the input sample-and-hold capacitors, inside
the “Input S/H” shown in the Block Diagram. At the instant
that CLK transitions from low to high, the sampled input is
held. While CLK is high, the held input voltage is buffered
by the S/H amplier which drives the rst pipelined ADC
stage. The rst stage acquires the output of the S/H dur-
ing this high phase of CLK. When CLK goes back low, the
rst stage produces its residue which is acquired by the
second stage. At the same time, the input S/H goes back to
acquiring the analog input. When CLK goes back high, the
second stage produces its residue which is acquired by the
third stage. An identical process is repeated for the third,
fourth and fth stages, resulting in a fth stage residue
that is sent to the sixth stage ADC for nal evaluation.
Each ADC stage following the rst has additional range to
accommodate ash and amplier offset errors. Results
from all of the ADC stages are digitally synchronized such
that the results can be properly combined in the correction
logic before being sent to the output buffer.
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC2285 CMOS
differential sample-and-hold. The analog inputs are con-
nectedtothesamplingcapacitors(CSAMPLE)throughNMOS
transistors. The capacitors shown attached to each input
(CPARASITIC) are the summation of all other capacitance
associated with each input.
During the sample phase when CLK is low, the transistors
connect the analog inputs to the sampling capacitors and
they charge to and track the differential input voltage. When
CLK transitions from low to high, the sampled input voltage
is held on the sampling capacitors. During the hold phase
when CLK is high, the sampling capacitors are disconnected
Figure 2. Equivalent Input Circuit
VDD
15Ω
CPARASITIC
1pF
CPARASITIC
1pF
CSAMPLE
3.5pF
CSAMPLE
3.5pF
LTC2285
AIN
+
AIN
–
CLK
2285 F02
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參數(shù)描述
LTC2285IUP-TR 制造商:LINER 制造商全稱:Linear Technology 功能描述:Dual 14-Bit, 125Msps Low Power 3V ADC
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LTC2286 制造商:LINER 制造商全稱:Linear Technology 功能描述:Dual 10-Bit, 65/40/25Msps Low Noise 3V ADCs
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