參數(shù)資料
型號: LTC2266IUJ-14#TRPBF
廠商: Linear Technology
文件頁數(shù): 9/32頁
文件大?。?/td> 0K
描述: IC ADC 14BIT 80MSPS DUAL 40QFN
標準包裝: 2,000
位數(shù): 14
采樣率(每秒): 80M
數(shù)據(jù)接口: Serial LVDS
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 257mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 40-WFQFN 裸露焊盤
供應商設(shè)備封裝: 40-QFN(6x6)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 Differential; 2 Single-Ended
配用: DC1371A-ND - BOARD USB DATA ACQUISITION HS
LTC2268-14/
LTC2267-14/LTC2266-14
17
22687614fa
become parallel logic inputs that control a reduced set of
the A/D operating modes. PAR/SER should be connected
directly to ground or the VDD of the part and not be driven
by a logic signal.
VREF(Pin36):ReferenceVoltageOutput.Bypasstoground
with a 1F ceramic capacitor, nominally 1.25V.
SENSE(Pin38):ReferenceProgrammingPin.Connecting
SENSEtoVDDselectstheinternalreferenceanda±1Vinput
range. Connecting SENSE to ground selects the internal
reference and a
±0.5V input range. An external reference
between 0.625V and 1.3V applied to SENSE selects an
input range of
±0.8 VSENSE.
LVDS Outputs
All pins below are differential LVDS outputs. The output
current level is programmable. There is an optional
internal 100Ω termination resistor between the pins of
each LVDS output pair.
OUT2B/OUT2B+, OUT2A/OUT2A+ (Pins 19/20, 21/22):
Serial Data Outputs for Channel 2. In 1-lane output mode
only OUT2A/OUT2A+ are used.
FR/FR+ (Pins 23/24): Frame Start Outputs.
DCO/DCO+ (Pins 27/28): Data Clock Outputs.
OUT1B/OUT1B+, OUT1A/OUT1A+ (Pins 29/30, 31/32):
Serial Data Outputs for Channel 1. In 1-lane output mode
only OUT1A/OUT1A+ are used.
pin FuncTions
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