參數(shù)資料
型號(hào): LTC2263CUJ-12#TRPBF
廠商: Linear Technology
文件頁(yè)數(shù): 21/34頁(yè)
文件大?。?/td> 0K
描述: IC ADC 12BIT SER/PAR 25M 40-QFN
標(biāo)準(zhǔn)包裝: 2,000
位數(shù): 12
采樣率(每秒): 25M
數(shù)據(jù)接口: Serial LVDS
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 146mW
電壓電源: 模擬和數(shù)字
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 40-WFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 40-QFN(6x6)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 Differential; 2 Single-Ended
配用: DC1532A-L-ND - BOARD DEMO 25MSPS LTC2263-12
DC1371A-ND - BOARD USB DATA ACQUISITION HS
28
22654312fb
LTC2265-12/
LTC2264-12/LTC2263-12
GROUNDING AND BYPASSING
The LTC2265-12/LTC2264-12/LTC2263-12 requires a
printed circuit board with a clean unbroken ground plane.
A multilayer board with an internal ground plane in the
first layer beneath the ADC is recommended. Layout for
the printed circuit board should ensure that digital and
analog signal lines are separated as much as possible. In
particular, care should be taken not to run any digital track
alongside an analog signal track or underneath the ADC.
High quality ceramic bypass capacitors should be used at
the VDD, OVDD, VCM, VREF, REFH and REFL pins. Bypass
capacitorsmustbelocatedasclosetothepinsaspossible.
Of particular importance is the 0.1F capacitor between
REFH and REFL. This capacitor should be on the same
side of the circuit board as the A/D, and as close to the
device as possible (1.5mm or less). Size 0402 ceramic
APPLICATIONS INFORMATION
capacitors are recommended. The larger 2.2F capacitor
between REFH and REFL can be somewhat further away.
Thetracesconnectingthepinsandbypasscapacitorsmust
be kept short and should be made as wide as possible.
The analog inputs, encode signals and digital outputs
should not be routed next to each other. Ground fill and
grounded vias should be used as barriers to isolate these
signals from each other.
HEAT TRANSFER
MostoftheheatgeneratedbytheLTC2265-12/LTC2264-12/
LTC2263-12 is transferred from the die through the bot-
tom-side Exposed Pad and package leads onto the printed
circuitboard.Forgoodelectricalandthermalperformance,
the Exposed Pad must be soldered to a large grounded
pad on the PC board. This pad should be connected to the
internal ground planes by an array of vias.
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