參數(shù)資料
型號(hào): LTC2261CUJ-12#TRPBF
廠商: Linear Technology
文件頁(yè)數(shù): 10/34頁(yè)
文件大?。?/td> 0K
描述: IC ADC 12BIT 125MSPS 40-QFN
產(chǎn)品培訓(xùn)模塊: LTC2262 - Ultra Low Power High Speed ADCs
標(biāo)準(zhǔn)包裝: 2,000
位數(shù): 12
采樣率(每秒): 125M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 146mW
電壓電源: 單電源
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 40-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 40-QFN(6x6)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個(gè)差分
配用: DC890B-ND - BOARD USB DATA COLLECTION
LTC2261-12
LTC2260-12/LTC2259-12
18
226112fc
For more information www.linear.com/LTC2261-12
CONVERTER OPERATION
TheLTC2261-12/LTC2260-12/LTC2259-12arelowpower
12-bit125Msps/105Msps/80MspsA/Dconvertersthatare
poweredbyasingle1.8Vsupply.Theanaloginputsshould
be driven differentially. The encode input can be driven
differentially or single ended for lower power consump-
tion. The digital outputs can be CMOS, double-data rate
CMOS(tohalvethenumberofoutputlines),ordouble-data
rate LVDS (to reduce digital noise in the system.) Many
additional features can be chosen by programming the
mode control registers through a serial SPI port. See the
Serial Programming Mode section.
ANALOG INPUT
The analog input is a differential CMOS sample-and-hold
circuit (Figure 2). The inputs should be driven differentially
around a common mode voltage set by the VCM output
pin, which is nominally VDD/2. For the 2V input range,
the inputs should swing from VCM – 0.5V to VCM + 0.5V.
Thereshouldbe180°phasedifferencebetweentheinputs.
INPUT DRIVE CIRCUITS
Input Filtering
If possible, there should be an RC lowpass filter right at
the analog inputs. This lowpass filter isolates the drive
circuitry from the A/D sample-and-hold switching, and
alsolimitswidebandnoisefromthedrivecircuitry.Figure 3
shows an example of an input RC filter. The RC component
values should be chosen based on the application’s input
frequency.
Transformer Coupled Circuits
Figure 3 shows the analog input being driven by an RF
transformer with a center-tapped secondary. The center
tap is biased with VCM, setting the A/D input at its optimal
DC level. At higher input frequencies a transmission line
CSAMPLE
3.5pF
RON
25
RON
25
VDD
LTC2261-12
AIN+
226112 F02
CSAMPLE
3.5pF
VDD
AIN–
ENC
ENC+
1.2V
10k
1.2V
10k
CPARASITIC
1.8pF
CPARASITIC
1.8pF
10
25
50
0.1F
AIN+
AIN–
12pF
0.1F
VCM
LTC2261-12
ANALOG
INPUT
0.1F
T1
1:1
T1: MA/COM MABAES0060
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
226112 F03
Figure 2. Equivalent Input Circuit
Figure 3. Analog Input Circuit Using a Transformer.
Recommended for Input Frequencies from 5MHz to 70MHz
applicaTions inForMaTion
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