參數(shù)資料
型號(hào)： LTC2260IUJ-14#TRPBF
廠商： LINEAR TECHNOLOGY CORP
元件分類： ADC
英文描述： 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40
封裝： 6 X 6 MM, LEAD FREE, PLASTIC, QFN-40
文件頁(yè)數(shù)： 29/32頁(yè)
文件大?。?/td> 431K
代理商： LTC2260IUJ-14#TRPBF
LTC2261-14
LTC2260-14/LTC2259-14
6
226114fa
POWER REQUIREMENTS The l denotes the specications which apply over the full operating temperature
range, otherwise specications are at TA = 25°C. (Note 9)
SYMBOL PARAMETER
CONDITIONS
LTC2261-14
LTC2260-14
LTC2259-14
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
CMOS Output Modes: Full Data Rate and Double-Data Rate
VDD
Analog Supply Voltage
(Note 10)
l
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
V
OVDD
Output Supply Voltage
(Note 10)
l
1.1
1.9
1.1
1.9
1.1
1.9
V
IVDD
Analog Supply Current
DC Input
Sine Wave Input
l
70.5
71.8
83.2
58.6
59.8
69.1
49.2
50.2
58.1
mA
IOVDD
Digital Supply Current
Sine Wave Input, OVDD=1.2V
3.9
3.3
2.5
mA
PDISS
Power Dissipation
DC Input
Sine Wave Input, OVDD=1.2V
l
127
134
150
106
112
125
89
93
105
mW
LVDS Output Mode
VDD
Analog Supply Voltage
(Note 10)
l
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
V
OVDD
Output Supply Voltage
(Note 10)
l
1.7
1.9
1.7
1.9
1.7
1.9
V
IVDD
Analog Supply Current
Sine Wave Input
l
75.4
89
63.4
74.8
53.8
63.5
mA
IOVDD
Digital Supply Current
(0VDD = 1.8V)
Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
l
20.7
40.5
26
47.8
20.7
40.5
26
47.8
20.7
40.5
26
47.8
mA
PDISS
Power Dissipation
Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
l
173
209
207
246
151
187
182
221
134
170
161
201
mW
All Output Modes
PSLEEP
Sleep Mode Power
0.5
mW
PNAP
Nap Mode Power
9
mW
PDIFFCLK
Power Increase with Differential Encode Mode Enabled
(No increase for Nap or Sleep Modes)
10
mW
TIMING CHARACTERISTICS The l denotes the specications which apply over the full operating temperature
range, otherwise specications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
LTC2261-14
LTC2260-14
LTC2259-14
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
fS
Sampling Frequency
(Note 10)
l
1
125
1
105
1
80
MHz
tL
ENC Low Time (Note 8)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
3.8
2.0
4
500
4.52
2.00
4.76
500
5.93
2.00
6.25
500
ns
tH
ENC High Time (Note 8)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
3.8
2.0
4
500
4.52
2.00
4.76
500
5.93
2.00
6.25
500
ns
tAP
Sample-and-Hold
Acquisition Delay Time
000
ns
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Digital Data Outputs (CMOS Modes: Full Data Rate and Double-Data Rate)
tD
ENC to Data Delay
CL = 5pF (Note 8)
l
1.1
1.7
3.1
ns
tC
ENC to CLKOUT Delay
CL = 5pF (Note 8)
l
1
1.4
2.6
ns
tSKEW
DATA to CLKOUT Skew
tD – tC (Note 8)
l
0
0.3
0.6
ns
Pipeline Latency
Full Data Rate Mode
Double-Data Rate Mode
5.0
5.5
Cycles
相關(guān)PDF資料
PDF描述
LTC2262CUJ-14#TRPBF 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40
LTC2262IUJ-14#PBF 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40
LTC2262IUJ-14#TRPBF 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40
LTC2262CUJ-14#PBF 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40
LTC2262IUJ-12#PBF 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LTC2260UJ-12 制造商:LINER 制造商全稱:Linear Technology 功能描述:12-Bit, 125/105/80Msps Ultralow Power 1.8V ADCs
LTC2260UJ-14 制造商:LINER 制造商全稱:Linear Technology 功能描述:14-Bit, 125/105/80Msps Ultralow Power 1.8V ADCs
LTC2261-12 制造商:LINER 制造商全稱:Linear Technology 功能描述:12-Bit, 125/105/80Msps Ultralow Power 1.8V ADCs
LTC2261-14 制造商:LINER 制造商全稱:Linear Technology 功能描述:16-Bit, 65Msps/40Msps/25Msps Low Power Dual ADCs
LTC2261CUJ-12#PBF 功能描述:IC ADC 12-BIT 125MSPS 40-QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個(gè)單端，單極；2 個(gè)差分，單極 產(chǎn)品目錄頁(yè)面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6
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