參數(shù)資料
型號： LTC2260CUJ-12#PBF
廠商： LINEAR TECHNOLOGY CORP
元件分類： ADC
英文描述： 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40
封裝： 6 X 6 MM, LEAD FREE, PLASTIC, QFN-40
文件頁數(shù)： 15/32頁
文件大小： 790K
代理商： LTC2260CUJ-12#PBF
LTC2261-12
LTC2260-12/LTC2259-12
22
226112fa
Overow Bit
The overow output bit (OF) outputs a logic high when
the analog input is either overranged or underranged.
The overow bit has the same pipeline latency as the
data bits.
Phase Shifting the Output Clock
In full-rate CMOS mode the data output bits normally
change at the same time as the falling edge of CLKOUT+,
so the rising edge of CLKOUT+ can be used to latch the
output data. In double-data rate CMOS and LVDS modes
the data output bits normally change at the same time as
the falling and rising edges of CLKOUT+. To allow adequate
setup-and-hold time when latching the data, the CLKOUT+
signal may need to be phase shifted relative to the data
output bits. Most FPGAs have this feature; this is generally
the best place to adjust the timing.
The LTC2261-12/LTC2260-12/LTC2259-12 can also phase
shift the CLKOUT+/CLKOUT– signals by serially program-
ming mode control register A2. The output clock can be
shifted by 0°, 45°, 90° or 135°. To use the phase shifting
feature the clock duty cycle stabilizer must be turned
on. Another control register bit can invert the polarity of
CLKOUT+ and CLKOUT–, independently of the phase shift.
The combination of these two features enables phase shifts
of 45° up to 315° (Figure 14).
DATA FORMAT
Table 1 shows the relationship between the analog input
voltage, the digital data output bits and the overow bit.
By default the output data format is offset binary. The 2’s
complement format can be selected by serially program-
ming mode control register A4.
Table 1. Output Codes vs Input Voltage
AIN+ – AIN–
(2V RANGE)
OF
D11-D0
(OFFSET BINARY)
D11-D0
(2’s COMPLEMENT)
>+1.000000V
+0.999512V
+0.999024V
1
0
1111 1111 1111
1111 1111 1110
0111 1111 1111
0111 1111 1110
+0.000488V
0.000000V
–0.000488V
–0.000976V
0
1000 0000 0001
1000 0000 0000
0111 1111 1111
0111 1111 1110
0000 0000 0001
0000 0000 0000
1111 1111 1111
1111 1111 1110
–0.999512V
–1.000000V
≤–1.000000V
0
1
0000 0000 0001
0000 0000 0000
1000 0000 0001
1000 0000 0000
APPLICATIONS INFORMATION
CLKOUT+
D0-D11, OF
PHASE
SHIFT
0°
45°
90°
135°
180°
225°
270°
315°
CLKINV
0
1
CLKPHASE1
MODE CONTROL BITS
0
1
0
1
CLKPHASE0
0
1
0
1
0
1
0
1
226112 F14
ENC+
Figure 14. Phase Shifting CLKOUT
相關(guān)PDF資料
PDF描述
LTC2259IUJ-14#PBF 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40
LTC2260CUJ-14#PBF 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40
LTC2260CUJ-14#TRPBF 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40
LTC2260IUJ-14#PBF 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40
LTC2259IUJ-14#TRPBF 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LTC2260CUJ-12-TRPBF 制造商:LINER 制造商全稱:Linear Technology 功能描述:12-Bit, 125/105/80Msps Ultralow Power 1.8V ADCs
LTC2260CUJ-14#PBF 功能描述:IC ADC 14-BIT 105MSPS 40-QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極
LTC2260CUJ-14#TRPBF 功能描述:IC ADC 14BIT 105MSPS 40-QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極
LTC2260CUJ-14-PBF 制造商:LINER 制造商全稱:Linear Technology 功能描述:14-Bit, 125/105/80Msps Ultralow Power 1.8V ADCs
LTC2260CUJ-14-TRPBF 制造商:LINER 制造商全稱:Linear Technology 功能描述:14-Bit, 125/105/80Msps Ultralow Power 1.8V ADCs
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