參數(shù)資料
型號(hào): LTC2259IUJ-16#TRPBF
廠商: LINEAR TECHNOLOGY CORP
元件分類: ADC
英文描述: PROPRIETARY METHOD ADC, PQCC40
封裝: 6 X 6 MM, LEAD FREE, PLASTIC, QFN-40
文件頁(yè)數(shù): 13/28頁(yè)
文件大?。?/td> 318K
代理商: LTC2259IUJ-16#TRPBF
LTC2259-16
20
225916f
The digital output is decoded at the receiver by inverting
the odd bits (D1, D3, D5, D7, D9, D11, D13, D15). The
alternate bit polarity mode is independent of the digital
output randomizer—either, both or neither function can
be on at the same time. When alternate bit polarity mode
is on, the data format is offset binary and the 2’s comple-
ment control bit has no effect. The alternate bit polarity
mode is enabled by serially programming mode control
register A4.
Digital Output Test Patterns
To allow in-circuit testing of the digital interface to the
A/D, there are several test modes that force most of the
A/D data outputs (D15-D2) to known values. Note that the
two LSBs, D1 and D0, are not controlled in the test pattern
mode and can have unknown values.
All 1s: Outputs are 1111 1111 1111 11XX
All 0s: Outputs are 0000 0000 0000 00XX
Alternating: On alternating samples, the outputs
change from 1111 1111 1111 11XX to 0000 0000
0000 00XX.
Checkerboard: On alternating samples, the outputs
change from 1010 1010 1010 10XX to 0101 0101
0101 01XX.
The digital output test patterns are enabled by serially
programming mode control register A4. When enabled,
the test patterns override all other formatting modes: 2’s
complement, randomizer, alternate-bit-polarity.
Output Disable
The digital outputs may be disabled by serially program-
ming mode control register A3. All digital outputs including
CLKOUT are disabled. The high impedance disabled state
is intended for long periods of inactivity—it is too slow
to multiplex a data bus between multiple converters at
full speed.
Sleep and Nap Modes
The A/D may be placed in sleep or nap modes to conserve
power. In sleep mode the entire A/D converter is powered
down, resulting in 0.5mW power consumption. Sleep mode
is enabled by mode control register A1 (serial program-
ming mode), or by SDI (parallel programming mode).
The amount of time required to recover from sleep mode
depends on the size of the bypass capacitors on VREF,
REFH, and REFL. For the suggested values in Figure 8,
the A/D will stabilize after 2ms.
In nap mode the A/D core is powered down while the
internal reference circuits stay active, allowing faster
wake-up than from sleep mode. Recovering from nap
mode requires at least 100 clock cycles. If the application
demands very accurate DC settling then an additional
50μs should be allowed so the on-chip references can
settle from the slight temperature shift caused by the
change in supply current as the A/D leaves nap mode.
Nap mode is enabled by mode control register A1 in the
serial programming mode.
DEVICE PROGRAMMING MODES
The operating modes of the LTC2259-16 can be pro-
grammed by either a parallel interface or a simple serial
interface. The serial interface has more exibility and
can program all available modes. The parallel interface
is more limited and can only program some of the more
commonly used modes.
Parallel Programming Mode
To use the parallel programming mode, PAR/SER should
be tied to VDD. The CS, SCK and SDI pins are binary logic
inputs that set certain operating modes. These pins can
be tied to VDD or ground, or driven by 1.8V, 2.5V or 3.3V
CMOS logic. Table 2 shows the modes set by CS, SCK
and SDI.
Table 2. Parallel Programming Mode Control Bits (PAR/SER = VDD)
PIN
DESCRIPTION
CS
Clock Duty Cycle Stabilizer Control Bit
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
SCK
Digital Output Mode Control Bit
0 = Full-Rate CMOS Output Mode
1 = Double-Data Rate LVDS Output Mode
(3.5mA LVDS Current, Internal Termination Off)
SDI
Power Down Control Bit
0 = Normal Operation
1 = Sleep Mode
APPLICATIONS INFORMATION
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