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參數(shù)資料
| 型號： | LTC2259IUJ-14#TRPBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40 |
| 封裝： | 6 X 6 MM, LEAD FREE, PLASTIC, QFN-40 |
| 文件頁數(shù)： | 7/32頁 |
| 文件大小： | 431K |
| 代理商： | LTC2259IUJ-14#TRPBF |
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15
226114fa
LTC2261-14
LTC2260-14/LTC2259-14
PIN FUNCTIONS
operating modes. PAR/SER should be connected directly
to ground or the VDD of the part and not be driven by a
logic signal.
VDD (Pins 9, 10, 40): 1.8V Analog Power Supply. Bypass
to ground with 0.1μF ceramic capacitors. Pins 9 and 10
can share a bypass capacitor.
ENC+ (Pin 11): Encode Input. Conversion starts on the
rising edge.
ENC– (Pin 12): Encode Complement Input. Conversion
starts on the falling edge.
CS (Pin 13): In serial programming mode, (PAR/SER =
0V), CS is the serial interface chip select input. When
CS is low, SCK is enabled for shifting data on SDI into
the mode control registers. In the parallel programming
mode (PAR/SER = VDD), CS controls the clock duty cycle
stabilizer. When CS is low, the clock duty cycle stabilizer is
turned off. When CS is high, the clock duty cycle stabilizer
is turned on. CS can be driven with 1.8V to 3.3V logic.
SCK (Pin 14): In serial programming mode, (PAR/SER =
0V), SCK is the serial interface clock input. In the parallel
programming mode (PAR/SER = VDD), SCK controls the
digital output mode. When SCK is low, the full-rate CMOS
output mode is enabled. When SCK is high, the double-
data rate LVDS output mode (with 3.5mA output current)
is enabled. SCK can be driven with 1.8V to 3.3V logic.
SDI (Pin 15): In serial programming mode, (PAR/SER =
0V), SDI is the serial interface data input. Data on SDI is
clocked into the mode control registers on the rising edge
of SCK. In the parallel programming mode (PAR/SER =
VDD), SDI can be used to power down the part. When SDI
is low, the part operates normally. When SDI is high, the
part enters sleep mode. SDI can be driven with 1.8V to
3.3V logic.
SDO (Pin 16): In serial programming mode, (PAR/SER
= 0V), SDO is the optional serial interface data output.
Data on SDO is read back from the mode control registers
and can be latched on the falling edge of SCK. SDO is an
open-drain NMOS output that requires an external 2k
pull-up resistor to 1.8V-3.3V. If read back from the mode
control registers is not needed, the pull-up resistor is not
necessary and SDO can be left unconnected. In the parallel
programming mode (PAR/SER = VDD), SDO is not used
and should not be connected.
OGND (Pin 25): Output Driver Ground.
OVDD (Pin 26): Output Driver Supply. Bypass to ground
with a 0.1μF ceramic capacitor.
VCM (Pin 37): Common Mode Bias Output, Nominally
Equal to VDD/2. VCM should be used to bias the common
mode of the analog inputs. Bypass to ground with a 0.1μF
ceramic capacitor.
VREF (Pin38):ReferenceVoltageOutput.Bypasstoground
with a 1μF ceramic capacitor, nominally 1.25V.
SENSE (Pin 39): Reference Programming Pin. Connecting
SENSE to VDD selects the internal reference and a ±1V input
range. Connecting SENSE to ground selects the internal
reference and a ±0.5V input range. An external reference
between 0.625V and 1.3V applied to SENSE selects an
input range of ±0.8 VSENSE.
FULL-RATE CMOS OUTPUT MODE
All Pins Below Have CMOS Output Levels (OGND to
OVDD)
D0 to D13 (Pins 17-24, 29-34): Digital Outputs. D13 is
the MSB.
CLKOUT– (Pin 27):
Inverted Version of CLKOUT+.
CLKOUT+ (Pin 28):
Data Output Clock. The digital outputs
normally transition at the same time as the falling edge
of CLKOUT+. The phase of CLKOUT+ can also be delayed
relative to the digital outputs by programming the mode
control registers.
DNC (Pin 35): Do not connect this pin.
OF (Pin 36): Over/Under Flow Digital Output. OF is high
when an overow or underow has occurred.
DOUBLE-DATA RATE CMOS OUTPUT MODE
All Pins Below Have CMOS Output Levels (OGND to
OVDD)
D0_1 to D12_13 (Pins 18, 20, 22, 24, 30, 32, 34): Double-
Data Rate Digital Outputs. Two data bits are multiplexed onto
each output pin. The even data bits (D0, D2, D4, D6, D8, D10,
相關(guān)PDF資料 |
PDF描述 |
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| LTC2259CUJ-14#PBF | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40 |
| LTC2259CUJ-14#TRPBF | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40 |
| LTC2260IUJ-14#TRPBF | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40 |
| LTC2262CUJ-14#TRPBF | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40 |
| LTC2262IUJ-14#PBF | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LTC2259IUJ-16 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:16-Bit, 80Msps Ultralow Power 1.8V ADC |
| LTC2259IUJ-16#PBF | 制造商:Linear Technology 功能描述:ADC Single Pipelined 80Msps 16-bit Parallel/LVDS 40-Pin QFN EP 制造商:Linear Technology 功能描述:IC ADC 16BIT 80MSPS 40QFN |
| LTC2259IUJ-16#TRPBF | 制造商:Linear Technology 功能描述:ADC Single Pipelined 80Msps 16-bit Parallel/LVDS 40-Pin QFN EP T/R 制造商:Linear Technology 功能描述:IC ADC 16BIT 80MSPS 40QFN |
| LTC2259IUJ-16PBF | 制造商:LINER 制造商全稱:Linear Technology 功能描述:16-Bit, 80Msps Ultralow Power 1.8V ADC |
| LTC2259IUJ-16TRPBF | 制造商:LINER 制造商全稱:Linear Technology 功能描述:16-Bit, 80Msps Ultralow Power 1.8V ADC |
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