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參數(shù)資料
| 型號： | LTC2259IUJ-12#TRPBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40 |
| 封裝： | 6 X 6 MM, LEAD FREE, PLASTIC, QFN-40 |
| 文件頁數(shù)： | 14/32頁 |
| 文件大?。?/td> | 790K |
| 代理商： | LTC2259IUJ-12#TRPBF |
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LTC2261-12
LTC2260-12/LTC2259-12
21
226112fa
APPLICATIONS INFORMATION
For applications where the sample rate needs to be changed
quickly, the clock duty cycle stabilizer can be disabled. If
the duty cycle stabilizer is disabled, care should be taken to
make the sampling clock have a 50%(±5%) duty cycle. The
duty cycle stabilizer should not be used below 5Msps.
DIGITAL OUTPUTS
Digital Output Modes
The LTC2261-12/LTC2260-12/LTC2259-12 can operate in
three digital output modes: full-rate CMOS, double-data
rate CMOS (to halve the number of output lines), or double-
data rate LVDS (to reduce digital noise in the system). The
output mode is set by mode control register A3 (serial
programming mode), or by SCK (parallel programming
mode). Note that double-data rate CMOS cannot be selected
in the parallel programming mode.
Full-Rate CMOS Mode
In full-rate CMOS mode the 12 digital outputs (D0-D11),
overow (OF), and the data output clocks (CLKOUT+,
CLKOUT–) have CMOS output levels. The outputs are
powered by OVDD and OGND which are isolated from the
A/D core power and ground. OVDD can range from 1.1V to
1.9V, allowing 1.2V through 1.8V CMOS logic outputs.
For good performance the digital outputs should drive
minimal capacitive loads. If the load capacitance is larger
than 10pF a digital buffer should be used.
Double-Data Rate CMOS Mode
In double-data rate CMOS mode, two data bits are mul-
tiplexed and output on each data pin. This reduces the
number of data lines by seven, simplifying board routing
and reducing the number of input pins needed to receive
the data. The 6 digital outputs (D0_1, D2_3, D4_5, D6_7,
D8_9, D10_11), overow (OF), and the data output clocks
(CLKOUT+, CLKOUT–) have CMOS output levels. The out-
puts are powered by OVDD and OGND which are isolated
from the A/D core power and ground. OVDD can range
from 1.1V to 1.9V, allowing 1.2V through 1.8V CMOS
logic outputs.
For good performance the digital outputs should drive
minimal capacitive loads. If the load capacitance is larger
than 10pF a digital buffer should be used.
When using double-data rate CMOS at high sample rates
the SNR will degrade slightly (see Typical Performance
Characteristics section). DDR CMOS is not recommended
for sample frequencies above 100MHz.
Double-Data Rate LVDS Mode
In double-data rate LVDS mode, two data bits are
multiplexed and output on each differential output pair.
There are 6 LVDS output pairs (D0_1+/D0_1– through
D10_11+/D10_11–) for the digital output data. Overow
(OF+/OF–) and the data output clock (CLKOUT+/CLKOUT–)
each have an LVDS output pair.
By default the outputs are standard LVDS levels: 3.5mA
output current and a 1.25V output common mode volt-
age. An external 100Ω differential termination resistor
is required for each LVDS output pair. The termination
resistors should be located as close as possible to the
LVDS receiver.
The outputs are powered by OVDD and OGND which are
isolated from the A/D core power and ground. In LVDS
mode, OVDD must be 1.8V.
Programmable LVDS Output Current
In LVDS mode, the default output driver current is 3.5mA.
This current can be adjusted by serially programming mode
control register A3. Available current levels are 1.75mA,
2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA.
Optional LVDS Driver Internal Termination
In most cases using just an external 100Ω termination
resistor will give excellent LVDS signal integrity. In addi-
tion, an optional internal 100Ω termination resistor can
be enabled by serially programming mode control register
A3. The internal termination helps absorb any reections
caused by imperfect termination at the receiver. When the
internal termination is enabled, the output driver current
is increased by 1.6x to maintain about the same output
voltage swing.
相關(guān)PDF資料 |
PDF描述 |
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| LTC2259IUJ-12#PBF | 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40 |
| LTC2259CUJ-12#TRPBF | 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40 |
| LTC2259CUJ-12#PBF | 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40 |
| LTC2260IUJ-12#TRPBF | 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40 |
| LTC2260IUJ-12#PBF | 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LTC2259IUJ-14 | 制造商:Linear Technology 功能描述:Single ADC Pipelined 80Msps 14-bit Parallel/LVDS 40-Pin QFN EP |
| LTC2259IUJ-14#PBF | 功能描述:IC ADC 14-BIT 80MSPS 40-QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| LTC2259IUJ-14#TRPBF | 功能描述:IC ADC 14BIT 80MSPS 40-QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| LTC2259IUJ-14-PBF | 制造商:LINER 制造商全稱:Linear Technology 功能描述:14-Bit, 125/105/80Msps Ultralow Power 1.8V ADCs |
| LTC2259IUJ-14-TRPBF | 制造商:LINER 制造商全稱:Linear Technology 功能描述:14-Bit, 125/105/80Msps Ultralow Power 1.8V ADCs |
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