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參數(shù)資料
| 型號： | LTC2246IUH#TR |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC32 |
| 封裝： | 5 X 5 MM, PLASTIC, MO-220WHHD-X, QFN-32 |
| 文件頁數(shù)： | 20/24頁 |
| 文件大?。?/td> | 771K |
| 代理商： | LTC2246IUH#TR |
LTC2248/LTC2247/LTC2246
5
224876fa
TI I G CHARACTERISTICS
U
W
The
● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: VDD = 3V, fSAMPLE = 65MHz (LTC2248), 40MHz (LTC2247), or
25MHz (LTC2246), input range = 2VP-P with differential drive, unless
otherwise noted.
Note 5: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 6: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 00 0000 0000 0000 and
11 1111 1111 1111.
Note 7: Guaranteed by design, not subject to test.
Note 8: VDD = 3V, fSAMPLE = 65MHz (LTC2248), 40MHz (LTC2247), or
25MHz (LTC2246), input range = 1VP-P with differential drive.
Note 9: Recommended operating conditions.
LTC2248
LTC2247
LTC2246
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
fs
Sampling Frequency (Note 9)
●
165
140
125
MHz
tL
CLK Low Time
Duty Cycle Stabilizer Off
●
7.3
7.7
500
11.8
12.5
500
18.9
20
500
ns
Duty Cycle Stabilizer On
●
5
7.7
500
5
12.5
500
5
20
500
ns
(Note 7)
tH
CLK High Time
Duty Cycle Stabilizer Off
●
7.3
7.7
500
11.8
12.5
500
18.9
20
500
ns
Duty Cycle Stabilizer On
●
5
7.7
500
5
12.5
500
5
20
500
ns
(Note 7)
tAP
Sample-and-Hold
0
ns
Aperture Delay
tD
CLK to DATA delay
CL = 5pF (Note 7)
●
1.4
2.7
5.4
1.4
2.7
5.4
1.4
2.7
5.4
ns
Data Access Time
CL = 5pF (Note 7)
●
4.3
10
4.3
10
4.3
10
ns
After OE
↓
BUS Relinquish Time (Note 7)
●
3.3
8.5
3.3
8.5
3.3
8.5
ns
Pipeline
5
Cycles
Latency
LTC2248: Typical DNL,
2V Range, 65Msps
LTC2248: Typical INL,
2V Range, 65Msps
CODE
0
INL
ERROR
(LSB)
12288
2248 G01
4096
8192
16384
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
CODE
0
DNL
ERROR
(LSB)
12288
2248 G02
4096
8192
16384
1.00
0.75
0.50
0.25
0
–0.25
–0.50
–0.75
–1.00
TYPICAL PERFOR A CE CHARACTERISTICS
UW
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