參數(shù)資料
型號: LTC2246HLU#TRPBF
廠商: LINEAR TECHNOLOGY CORP
元件分類: ADC
英文描述: 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP32
封裝: 5 X 5 MM, LEAD FREE, PLASTIC, MS-026, TQFP-32
文件頁數(shù): 3/16頁
文件大?。?/td> 273K
代理商: LTC2246HLU#TRPBF
LTC2246H
11
2246hf
Input Drive Impedance
As with all high performance, high speed ADCs, the dy-
namic performance of the LTC2246H can be inuenced by
the input drive circuitry, particularly the second and third
harmonics. Source impedance and reactance can inuence
SFDR. At the falling edge of CLK, the sample-and-hold
circuit will connect the 4pF sampling capacitor to the input
pin and start the sampling period. The sampling period
ends when CLK rises, holding the sampled input on the
sampling capacitor. Ideally the input circuitry should be
fast enough to fully charge the sampling capacitor during
the sampling period 1/(2FENCODE); however, this is not
always possible and the incomplete settling may degrade
the SFDR. The sampling glitch has been designed to be
as linear as possible to minimize the effects of incomplete
settling.
For the best performance, it is recommended to have a
source impedance of 100Ω or less for each input. The
source impedance should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
Input Drive Circuits
Figure 3 shows the LTC2246H being driven by an RF
transformer with a center tapped secondary. The secondary
center tap is DC biased with VCM, setting the ADC input
signal at its optimum DC level. Terminating on the trans-
former secondary is desirable, as this provides a common
mode path for charging glitches caused by the sample and
hold. Figure 3 shows a 1:1 turns ratio transformer. Other
turns ratios can be used if the source impedance seen
by the ADC does not exceed 100Ω for each ADC input.
A disadvantage of using a transformer is the loss of low
frequency response. Most small RF transformers have
poor performance at frequencies below 1MHz.
Figure 4 demonstrates the use of a differential amplier to
convert a single ended input signal into a differential input
signal. The advantage of this method is that it provides
low frequency input response; however, the limited gain
bandwidth of most op amps will limit the SFDR at high
input frequencies.
Figure 5 shows a single-ended input circuit. The impedance
seen by the analog inputs should be matched. This circuit
is not recommended if low distortion is required.
The 25Ω resistors and 12pF capacitor on the analog
inputs serve two purposes: isolating the drive circuitry
from the sample-and-hold charging glitches and limiting
the wideband noise at the converter input.
APPLICATIONS INFORMATION
25Ω
0.1μF
AIN
+
AIN
12pF
2.2μF
VCM
LTC2246H
ANALOG
INPUT
0.1μFT1
1:1
T1 = MA/COM ETC1-1T
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
2246 F03
Figure 3. Single-Ended to Differential Conversion
Using a Transformer
25Ω
12pF
2.2μF
VCM
LTC2246H
2246 F04
+
CM
ANALOG
INPUT
HIGH SPEED
DIFFERENTIAL
AMPLIFIER
AIN
+
AIN
25Ω
0.1μF
ANALOG
INPUT
VCM
AIN
+
AIN
1k
12pF
2246 F05
2.2μF
1k
25Ω
0.1μF
LTC2246H
Figure 4. Differential Drive with an Amplier
Figure 5. Single-Ended Drive
相關(guān)PDF資料
PDF描述
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LTC2246HLU 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP32
LTC2246IUH 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC32
LTC2246IUH#TR 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC32
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