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參數(shù)資料
| 型號： | LTC2241CUP-10#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 11/28頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT 210MSPS 64-QFN |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 210M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 805mW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 64-QFN（9x9） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
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LTC2241-10
19
224110fb
APPLICATIONS INFORMATION
Maximum and Minimum Encode Rates
The maximum encode rate for the LTC2241-10 is 210Msps.
For the ADC to operate properly, the encode signal should
have a 50% (±5%) duty cycle. Each half cycle must have at
least 2.26ns for the ADC internal circuitry to have enough
settling time for proper operation. Achieving a precise 50%
duty cycle is easy with differential sinusoidal drive using
a transformer or using symmetric differential logic such
as PECL or LVDS.
An optional clock duty cycle stabilizer circuit can be used if
the input clock has a non 50% duty cycle. This circuit uses
the rising edge of the ENC+ pin to sample the analog input.
The falling edge of ENC+ is ignored and the internal falling
edge is generated by a phase-locked loop. The input clock
duty cycle can vary from 40% to 60% and the clock duty
cycle stabilizer will maintain a constant 50% internal duty
cycle. If the clock is turned off for a long period of time,
the duty cycle stabilizer circuit will require one hundred
clock cycles for the PLL to lock onto the input clock. To
use the clock duty cycle stabilizer, the MODE pin should be
connected to 1/3VDD or 2/3VDD using external resistors.
The lower limit of the LTC2241-10 sample rate is determined
by droop of the sample-and-hold circuits. The pipelined
architecture of this ADC relies on storing analog signals on
small valued capacitors. Junction leakage will discharge
the capacitors. The specied minimum operating frequency
for the LTC2241-10 is 1Msps.
DIGITAL OUTPUTS
Table 1 shows the relationship between the analog input
voltage, the digital data bits, and the overow bit.
Figure 11. Transformer Driven ENC+/ENC–
Figure 12a. Single-Ended ENC Drive,
Not Recommended for Low Jitter
Figure 12b. ENC Drive Using LVDS
VDD
LTC2241-10
224110 F11
VDD
ENC–
ENC+
1.5V BIAS
0.1μF
T1
MA/COM
ETC1-1-13
CLOCK
INPUT
100Ω
8.2pF
0.1μF
50Ω
50Ω
4.8k
TO INTERNAL
ADC CIRCUITS
224110 F12a
ENC–
1.5V
VTHRESHOLD = 1.5V
ENC+
0.1μF
LTC2241-10
224110 F12b
ENC–
ENC+
LVDS
CLOCK
100Ω
0.1μF
LTC2241-10
0.1μF
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LTC2241CUP-12 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:12-Bit, 210Msps ADC |
| LTC2241CUP-12#PBF | 制造商:Linear Technology 功能描述:ADC Single Pipelined 210Msps 12-bit Parallel/LVDS 64-Pin QFN EP 制造商:Linear Technology 功能描述:IC ADC 12BIT 210MSPS 64-QFN 制造商:Linear Technology 功能描述:IC, ADC, 12BIT, 210MSPS, QFN-64; Resolution (Bits):12bit; Sampling Rate:210MSPS; Supply Voltage Type:Single; Supply Voltage Min:2.375V; Supply Voltage Max:2.625V; Supply Current:226mA; Digital IC Case Style:QFN; No. of Pins:64 ;RoHS Compliant: Yes |
| LTC2241CUP-12#TRPBF | 制造商:Linear Technology 功能描述:ADC Single Pipelined 210Msps 12-bit Parallel/LVDS 64-Pin QFN EP T/R 制造商:Linear Technology 功能描述:IC ADC 12BIT 210MSPS 64-QFN |
| LTC2241CUP-12-PBF | 制造商:LINER 制造商全稱:Linear Technology 功能描述:12-Bit, 210Msps ADC |
| LTC2241CUP-12-TR | 制造商:LINER 制造商全稱:Linear Technology 功能描述:12-Bit, 210Msps ADC |
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