參數(shù)資料
型號: LTC2237
廠商: Linear Technology Corporation
英文描述: Replaced by SN74ALVCH16244 : 16-Bit Buffer/Driver With 3-State Outputs 48-TSSOP -40 to 85
中文描述: 14位,80Msps ADC的低功耗3V的
文件頁數(shù): 14/20頁
文件大?。?/td> 464K
代理商: LTC2237
LTC2249
14
2249f
The lower limit of the LTC2249 sample rate is determined
by droop of the sample-and-hold circuits. The pipelined
architecture of this ADC relies on storing analog signals on
small valued capacitors. Junction leakage will discharge
the capacitors. The specified minimum operating fre-
quency for the LTC2249 is 1Msps.
DIGITAL OUTPUTS
Digital Output Buffers
Figure 12 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OV
DD
and OGND, iso-
lated from the ADC power and ground. The additional
N-channel transistor in the output driver allows operation
down to low voltages. The internal resistor in series with
the output makes the output appear as 50
to external
circuitry and may eliminate the need for external damping
resistors.
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2249 should drive a minimal
capacitive load to avoid possible interaction between the
digital outputs and sensitive input circuitry. The output
should be buffered with a device such as an ALVCH16373
CMOS latch. For full speed operation the capacitive load
should be kept under 10pF.
Lower OV
DD
voltages will also help reduce interference
from the digital outputs.
Data Format
Using the MODE pin, the LTC2249 parallel digital output
can be selected for offset binary or 2’s complement
format. Connecting MODE to GND or 1/3V
DD
selects
straight binary output format. Connecting MODE to
2/3V
DD
or V
DD
selects 2’s complement output format.
An external resistor divider can be used to set the 1/3V
DD
or 2/3V
DD
logic values. Table 1 shows the logic states for
the MODE pin.
Figure 12. Digital Output Buffer
LTC2249
2249 F12
OV
DD
V
DD
V
DD
0.1
μ
F
43
TYPICAL
DATA
OUTPUT
OGND
OV
DD
0.5V
TO V
DD
PREDRIVER
LOGIC
DATA
FROM
LATCH
OE
Table 1. MODE Pin Function
Clock Duty
Cycle Stablizer
Off
On
On
Off
MODE Pin
0
1/3V
DD
2/3V
DD
V
DD
Output Format
Straight Binary
Straight Binary
2’s Complement
2’s Complement
Overflow Bit
When OF outputs a logic high the converter is either
overranged or underranged.
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OV
DD
, should be tied
to the same power supply as for the logic being driven. For
example if the converter is driving a DSP powered by a 1.8V
supply, then OV
DD
should be tied to that same 1.8V supply.
OV
DD
can be powered with any voltage from 500mV up to
the V
DD
of the part. OGND can be powered with any voltage
from GND up to 1V and must be less than OV
DD
. The logic
outputs will swing between OGND and OV
DD
.
Output Enable
The outputs may be disabled with the output enable pin, OE.
OE high disables all data outputs including OF. The data ac-
cess and bus relinquish times are too slow to allow the
outputs to be enabled and disabled during full speed op-
eration. The output Hi-Z state is intended for use during long
periods of inactivity.
APPLICATIOU
W
U
U
相關PDF資料
PDF描述
LTC2238 Replaced by SN74ALVCH16244 : 16-Bit Buffer/Driver With 3-State Outputs 48-SSOP -40 to 85
LTC2239 14-Bit, 80Msps Low Power 3V ADC
LTC2249CUH 14-Bit, 80Msps Low Power 3V ADC
LTC2284 Dual 14-Bit, 105Msps Low Power 3V ADC
LTC2284CUP Dual 14-Bit, 105Msps Low Power 3V ADC
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