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參數(shù)資料
| 型號(hào)： | LTC2234 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 16-Bit Universal Bus Driver With 3-State Outputs 48-SSOP -40 to 85 |
| 中文描述： | 14位，80Msps ADC的低功耗3V的 |
| 文件頁(yè)數(shù)： | 8/20頁(yè) |
| 文件大?。?/td> | 464K |
| 代理商： | LTC2234 |
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LTC2249
8
2249f
operation with the outputs enabled. Connecting SHDN to
GND and OE to V
DD
results in normal operation with the
outputs at high impedance. Connecting SHDN to V
DD
and
OE to GND results in nap mode with the outputs at high
impedance. Connecting SHDN to V
DD
and OE to V
DD
results in sleep mode with the outputs at high impedance.
OE (Pin 11):
Output Enable Pin. Refer to SHDN pin
function.
D0 – D13 (Pins 12, 13, 14, 15, 16, 17, 18, 19, 22, 23, 24,
25, 26, 27):
Digital Outputs. D13 is the MSB.
OGND (Pin 20):
Output Driver Ground.
OV
DD
(Pin 21):
Positive Supply for the Output Drivers.
Bypass to ground with 0.1
μ
F ceramic chip capacitor.
OF (Pin 28):
Over/Under Flow Output. High when an over
or under flow has occurred.
MODE (Pin 29):
Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to GND selects
straight binary output format and turns the clock duty
cycle stabilizer off. 1/3 V
DD
selects straight binary output
format and turns the clock duty cycle stabilizer on. 2/3 V
DD
selects 2’s complement output format and turns the clock
duty cycle stabilizer on. V
DD
selects 2’s complement
output format and turns the clock duty cycle stabilizer off.
SENSE (Pin 30):
Reference Programming Pin. Connecting
SENSE to V
CM
selects the internal reference and a
±
0.5V
input range. V
DD
selects the internal reference and a
±
1V
input range. An external reference greater than 0.5V and
less than 1V applied to SENSE selects an input range of
±
V
SENSE
.
±
1V is the largest valid input range.
V
CM
(Pin 31):
1.5V Output and Input Common Mode Bias.
Bypass to ground with 2.2
μ
F ceramic chip capacitor.
GND (Exposed Pad) (Pin 33):
ADC Power Ground. The
exposed pad on the bottom of the package needs to be
soldered to ground.
PIU
FU
CTIO
AL BLOCK DIAGRW
U
U
SHIFT REGISTER
AND CORRECTION
DIFF
REF
AMP
REF
BUF
2.2
μ
F
1
μ
F
1
μ
F
0.1
μ
F
INTERNAL CLOCK SIGNALS
REFH
REFL
CLOCK/DUTY
CYCLE
CONTROL
RANGE
SELECT
1.5V
REFERENCE
FIRST PIPELINED
ADC STAGE
FIFTH PIPELINED
ADC STAGE
SIXTH PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
REFH
REFL
CLK
OE
MODE
OGND
OV
DD
2249 F01
INPUT
S/H
SENSE
V
CM
A
IN–
A
IN+
2.2
μ
F
THIRD PIPELINED
ADC STAGE
OUTPUT
DRIVERS
CONTROL
LOGIC
SHDN
OF
D13
D0
Figure 1. Functional Block Diagram
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LTC2236 | 16-Bit Universal Bus Driver With 3-State Outputs 48-SSOP -40 to 85 |
| LTC2237 | Replaced by SN74ALVCH16244 : 16-Bit Buffer/Driver With 3-State Outputs 48-TSSOP -40 to 85 |
| LTC2238 | Replaced by SN74ALVCH16244 : 16-Bit Buffer/Driver With 3-State Outputs 48-SSOP -40 to 85 |
| LTC2239 | 14-Bit, 80Msps Low Power 3V ADC |
| LTC2249CUH | 14-Bit, 80Msps Low Power 3V ADC |
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