參數(shù)資料
型號: LTC2230CUP#PBF
廠商: Linear Technology
文件頁數(shù): 16/32頁
文件大?。?/td> 0K
描述: IC ADC 10BIT 170MSPS 64-QFN
標準包裝: 40
位數(shù): 10
采樣率(每秒): 170M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 1.18W
電壓電源: 單電源
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 64-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 64-QFN(9x9)
包裝: 管件
輸入數(shù)目和類型: 1 個單端,雙極; 1 個差分,雙極
LTC2230/LTC2231
23
22301fb
duty cycle. If the clock is turned off for a long period of
time, the duty cycle stabilizer circuit will require a hundred
clock cycles for the PLL to lock onto the input clock. To use
the clock duty cycle stabilizer, the MODE pin should be
connected to 1/3VDD or 2/3VDD using external resistors.
The lower limit of the LTC2230/LTC2231 sample rate is
determined by droop of the sample-and-hold circuits. The
pipelined architecture of this ADC relies on storing analog
signals on small valued capacitors. Junction leakage will
discharge the capacitors. The specified minimum operat-
ing frequency for the LTC2230/LTC2231 is 1Msps.
Digital Output Modes
The LTC2230/LTC2231 can operate in several digital out-
put modes: LVDS, CMOS running at full speed, and CMOS
demultiplexed onto two buses, each of which runs at half
speed. In the demultiplexed CMOS modes the two buses
(referred to as bus A and bus B) can either be updated on
alternate clock cycles (interleaved mode) or simultaneously
(simultaneous mode). For details on the clock timing, refer
to the timing diagrams.
The LVDS pin selects which digital output mode the part
uses. This pin has a four-level logic input which should be
connected to GND, 1/3VDD, 2/3VDD or VDD. An external
resistor divider can be used to set the 1/3VDD or 2/3VDD
logic values. Table 2 shows the logic states for the
LVDS pin.
APPLICATIO S I FOR ATIO
WU
UU
DIGITAL OUTPUTS
Table 1. Output Codes vs Input Voltage
AIN+ – AIN–
D9 – D0
(2V Range)
OF
(Offset Binary)
(2’s Complement)
>+1.000000V
1
11 1111 1111
01 1111 1111
+0.998047V
0
11 1111 1111
01 1111 1111
+0.996094V
0
11 1111 1110
01 1111 1110
+0.001953V
0
10 0000 0001
00 0000 0001
0.000000V
0
10 0000 0000
00 0000 0000
–0.001953V
0
01 1111 1111
11 1111 1111
–0.003906V
0
01 1111 1110
11 1111 1110
–0.998047V
0
00 0000 0001
10 0000 0001
–1.000000V
0
00 0000 0000
10 0000 0000
<–1.000000V
1
00 0000 0000
10 0000 0000
22301 F12a
ENC
1.6V
VTHRESHOLD = 1.6V
ENC+
0.1
μF
LTC2230/
LTC2231
22301 F12b
ENC
ENC+
130
Ω
3.3V
130
Ω
D0
Q0
MC100LVELT22
LTC2230/
LTC2231
83
Ω
83
Ω
Figure 12a. Single-Ended ENC Drive,
Not Recommended for Low Jitter
Figure 12b. ENC Drive Using a CMOS to PECL Translator
LTC2230/LTC2231
22301 F13a
OVDD
VDD
0.1
μF
43
Ω
TYPICAL
DATA
OUTPUT
OGND
OVDD
0.5V
TO 3.6V
PREDRIVER
LOGIC
DATA
FROM
LATCH
OE
Figure 13a. Digital Output Buffer in CMOS Mode
Table 2. LVDS Pin Function
LVDS
Digital Output Mode
GND
Full-Rate CMOS
1/3VDD
Demultiplexed CMOS, Simultaneous Update
2/3VDD
Demultiplexed CMOS, Interleaved Update
VDD
LVDS
Digital Output Buffers (CMOS Modes)
Figure 13a shows an equivalent circuit for a single output
buffer in the CMOS output mode. Each buffer is powered
by OVDD and OGND, isolated from the ADC power and
ground. The additional N-channel transistor in the output
driver allows operation down to low voltages. The internal
resistor in series with the output makes the output appear
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