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參數(shù)資料
| 型號： | LTC2226HLU#TRPBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP32 |
| 封裝： | 5 X 5 MM, LEAD FREE, PLASTIC, MS-026, TQFP-32 |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 679K |
| 代理商： | LTC2226HLU#TRPBF |
LTC2226H
2226hfa
Driving the Clock Input
The CLK input can be driven directly with a CMOS or TTL
level signal. A differential clock can also be used along
with a low-jitter CMOS converter before the CLK pin (see
Figure 8).
ThenoiseperformanceoftheLTC2226Hcandependonthe
clock signal quality as much as on the analog input. Any
noise present on the clock signal will result in additional
aperture jitter that will be RMS summed with the inherent
ADC aperture jitter.
Maximum and Minimum Conversion Rates
ThemaximumconversionratefortheLTC2226His25Msps.
For the ADC to operate properly, the CLK signal should
have a 50% (±5%) duty cycle. Each half cycle must have at
least 18.9ns for the ADC internal circuitry to have enough
settling time for proper operation.
An optional clock duty cycle stabilizer circuit can be used
if the input clock has a non 50% duty cycle. This circuit
uses the rising edge of the CLK pin to sample the analog
input. The falling edge of CLK is ignored and the internal
falling edge is generated by a phase-locked loop. The
input clock duty cycle can vary and the clock duty cycle
stabilizer will maintain a constant 50% internal duty cycle.
If the clock is turned off for a long period of time, the duty
cycle stabilizer circuit will require a hundred clock cycles
for the PLL to lock onto the input clock. To use the clock
duty cycle stabilizer, the MODE pin should be connected
to 1/3VDD or 2/3VDD using external resistors.
If the clock duty cycle stabilizer is used, a >1s high pulse
shouldbeappliedtotheSHDNpinoncethepowersupplies
are stable at power up.
The lower limit of the LTC2226H sample rate is determined
by droop of the sample-and-hold circuits. The pipelined
architecture of this ADC relies on storing analog signals on
small valued capacitors. Junction leakage will discharge
thecapacitors.Thespecifiedminimumoperatingfrequency
for the LTC2226H is 1Msps.
DIGITAL OUTPUTS
Table 1 shows the relationship between the analog input
voltage, the digital data bits, and the overflow bit.
Digital Output Buffers
Figure 9 shows an equivalent circuit for a single output
buffer.EachbufferispoweredbyOVDDandOGND,isolated
from the ADC power and ground. The additional
N-channel transistor in the output driver allows operation
down to low voltages. The internal resistor in series with
the output makes the output appear as 50
W to external
circuitry and may eliminate the need for external damping
resistors.
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2226H should drive a minimal
capacitive load to avoid possible interaction between the
digital outputs and sensitive input circuitry. The output
should be buffered with a device such as an ALVCH16373
CMOS latch. For full speed operation the capacitive load
should be kept under 10pF.
Lower OVDD voltages will also help reduce interference
from the digital outputs.
applicaTions inForMaTion
Table 1. Output Codes vs Input Voltage
AIN+ – AIN–
(2V Range)
OF
D11 – D0
(Offset Binary)
D11 – D0
(2’s Complement)
>+1.000000V
+0.999512V
+0.999024V
1
0
11 11 1111 1111
11 11 1111 1110
0111 1111 1111
0111 1111 1110
+0.000488V
0.000000V
–0.000488V
–0.000976V
0
10 00 0000 0001
10 00 0000 0000
01 11 1111 1111
01 11 1111 1110
00 00 0000 0001
00 00 0000 0000
11 11 1111 1111
11 11 1111 1110
–0.999512V
–1.000000V
<–1.000000V
0
1
0000 0000 0001
0000 0000 0000
1000 0000 0001
1000 0000 0000
LTC2226H
2226 F09
OVDD
VDD
0.1
F
43
TYPICAL
DATA
OUTPUT
OGND
OVDD 0.5V
TO 3.6V
PREDRIVER
LOGIC
DATA
FROM
LATCH
OE
Figure 9. Digital Output Buffer
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LTC2226HLU#TR | 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP32 |
| LTC2246HLU#PBF | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP32 |
| LTC2246HLU#TRPBF | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP32 |
| LTC2246HLU#TR | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP32 |
| LTC2246HLU | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP32 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LTC2226HLX | 制造商:LINER 制造商全稱:Linear Technology 功能描述:12-Bit, 25Msps 125°C ADC in LQFP |
| LTC2226HLX#PBF | 功能描述:IC ADC 12BIT 25MSPS 48-LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個單端，單極；1 個單端，雙極 |
| LTC2226HLX-PBF | 制造商:LINER 制造商全稱:Linear Technology 功能描述:12-Bit, 25Msps 125°C ADC in LQFP |
| LTC2226HLX-TR | 制造商:LINER 制造商全稱:Linear Technology 功能描述:12-Bit, 25Msps 125°C ADC in LQFP |
| LTC2226HLX-TRPBF | 制造商:LINER 制造商全稱:Linear Technology 功能描述:12-Bit, 25Msps 125°C ADC in LQFP |
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