參數(shù)資料
型號(hào): LTC2224IUK#TRPBF
廠(chǎng)商: Linear Technology
文件頁(yè)數(shù): 1/24頁(yè)
文件大?。?/td> 0K
描述: IC ADC 12BIT 135MSPS SAMPL 48QFN
標(biāo)準(zhǔn)包裝: 2,000
位數(shù): 12
采樣率(每秒): 135M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 680mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 48-WFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 48-QFN-EP(7x7)
包裝: 帶卷 (TR)
輸入數(shù)目和類(lèi)型: 1 個(gè)單端,雙極; 1 個(gè)差分,雙極
LTC2224
1
2224fa
FEATURES
DESCRIPTIO
U
TYPICAL APPLICATIO
U
Sample Rate: 135Msps
67.3dB SNR up to 140MHz Input
80dB SFDR up to 150MHz Input
775MHz Full Power Bandwidth S/H
Single 3.3V Supply
Low Power Dissipation: 630mW
CMOS Outputs
Selectable Input Ranges:
±0.5V or ±1V
No Missing Codes
Optional Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
Data Ready Output Clock
Pin Compatible Family
135Msps: LTC2224 (12-Bit), LTC2234 (10-Bit)
105Msps: LTC2222 (12-Bit), LTC2232 (10-Bit)
80Msps: LTC2223 (12-Bit), LTC2233 (10-Bit)
48-Pin 7mm
× 7mm QFN Package
Wireless and Wired Broadband Communication
Cable Head-End Systems
Power Amplifier Linearization
Communications Test Equipment
12-Bit, 135Msps ADC
The LTC
2224 is a 135Msps, sampling 12-bit A/D con-
verter designed for digitizing high frequency, wide dy-
namic range signals. The LTC2224 is perfect for demand-
ing communications applications with AC performance
that includes 67.3dB SNR and 80dB spurious free dy-
namic range for signals up to 150MHz. Ultralow jitter of
0.15psRMS allows undersampling of IF frequencies with
excellent noise performance.
DC specs include
±0.4LSB INL (typ), ±0.3LSB DNL (typ)
and no missing codes over temperature. The transition
noise is a low 0.5LSBRMS.
A separate output power supply allows the CMOS output
swing to range from 0.5V to 3.6V.
The ENC+ and ENCinputs may be driven differentially or
single ended with a sine wave, PECL, LVDS, TTL, or CMOS
inputs. An optional clock duty cycle stabilizer allows high
performance at full speed for a wide range of clock duty
cycles.
0.5V TO 3.6V
OVDD
OGND
+
INPUT
S/H
CORRECTION
LOGIC
OUTPUT
DRIVERS
12-BIT
PIPELINED
ADC CORE
CLOCK/DUTY
CYCLE
CONTROL
FLEXIBLE
REFERENCE
D11
D0
ENCODE
INPUT
REFH
REFL
ANALOG
INPUT
2224 TA01
3.3V
VDD
APPLICATIO S
U
SFDR vs Input Frequency
SFDR
(dBFS)
INPUT FREQUENCY (MHz)
0
600
500
400
2224 TA01b
100
200
300
95
90
85
80
75
70
65
60
55
50
4th OR HIGHER
2nd OR 3rd
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
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