參數(shù)資料
型號(hào)： LTC2222CUK
廠商： Linear Technology
文件頁(yè)數(shù)： 8/28頁(yè)
文件大小： 0K
描述： IC ADC 12BIT 105MSPS SAMPL 48QFN
標(biāo)準(zhǔn)包裝： 52
位數(shù)： 12
采樣率（每秒）： 105M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 535mW
電壓電源： 單電源
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 48-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 48-QFN-EP（7x7）
包裝： 管件
輸入數(shù)目和類型： 1 個(gè)單端，雙極; 1 個(gè)差分，雙極
LTC2222/LTC2223
16
22223fb
APPLICATIONS INFORMATION
CONVERTER OPERATION
As shown in Figure 1, the LTC2222/LTC2223 is a CMOS
pipelined multistep converter. The converter has ve pipe-
lined ADC stages; a sampled analog input will result in a
digitized value ve cycles later (see the Timing Diagram
section). For optimal AC performance the analog inputs
should be driven differentially. For cost sensitive applica-
tions, the analog inputs can be driven single-ended with
slightly worse harmonic distortion. The encode input is
differential for improved common mode noise immunity.
The LTC2222/LTC2223 has two phases of operation, de-
termined by the state of the differential ENC+/ENC– input
pins. For brevity, the text will refer to ENC+ greater than
ENC– as ENC high and ENC+ less than ENC– as ENC low.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage residue amplier.
In operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplied and
output by the residue amplier. Successive stages operate
out of phase so that when the odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
When ENC is low, the analog input is sampled differentially
directly onto the input sample-and-hold capacitors, inside
the “Input S/H” shown in the block diagram. At the instant
that ENC transitions from low to high, the sampled input is
held. While ENC is high, the held input voltage is buffered
by the S/H amplier which drives the rst pipelined ADC
stage. The rst stage acquires the output of the S/H dur-
ing this high phase of ENC. When ENC goes back low, the
rst stage produces its residue which is acquired by the
second stage. At the same time, the input S/H goes back
to acquiring the analog input. When ENC goes back high,
the second stage produces its residue which is acquired
by the third stage. An identical process is repeated for the
third and fourth stages, resulting in a fourth stage residue
that is sent to the fth stage ADC for nal evaluation.
Each ADC stage following the rst has additional range to
accommodate ash and amplier offset errors. Results
from all of the ADC stages are digitally synchronized such
that the results can be properly combined in the correction
logic before being sent to the output buffer.
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC2222/
LTC2223 CMOS differential sample-and-hold. The analog
inputs are connected to the sampling capacitors (CSAMPLE)
through NMOS transistors. The capacitors shown attached
to each input (CPARASITIC) are the summation of all other
capacitance associated with each input.
Figure 2. Equivalent Input Circuit
CSAMPLE
1.6pF
VDD
LTC2222/LTC2223
AIN
+
22223 F02
CSAMPLE
1.6pF
VDD
AIN
–
ENC–
ENC+
1.6V
6k
1.6V
6k
CPARASITIC
1pF
CPARASITIC
1pF
15Ω
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