common mode voltage of 1.6V. The V
參數(shù)資料
型號(hào)： LTC2220CUP#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 13/32頁(yè)
文件大?。?/td> 0K
描述： IC ADC 12BIT 170MSPS 64-QFN
標(biāo)準(zhǔn)包裝： 2,000
位數(shù)： 12
采樣率（每秒）： 170M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 1.18W
電壓電源： 單電源
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 64-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 64-QFN（9x9）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 1 個(gè)單端，雙極; 1 個(gè)差分，雙極
LTC2220/LTC2221
20
22201fa
the 2V range or
±0.25V for the 1V range, around a
common mode voltage of 1.6V. The VCM output pin (Pin
60) may be used to provide the common mode bias level.
VCM can be tied directly to the center tap of a transformer
to set the DC input level or as a reference level to an op amp
differential driver circuit. The VCM pin must be bypassed to
ground close to the ADC with a 2.2
F or greater capacitor.
Input Drive Impedance
As with all high performance, high speed ADCs, the
dynamic performance of the LTC2220/LTC2221 can be
influenced by the input drive circuitry, particularly the
second and third harmonics. Source impedance and input
reactance can influence SFDR. At the falling edge of ENC,
the sample-and-hold circuit will connect the 1.6pF sam-
pling capacitor to the input pin and start the sampling
period. The sampling period ends when ENC rises, holding
the sampled input on the sampling capacitor. Ideally the
input circuitry should be fast enough to fully charge
the sampling capacitor during the sampling period
1/(2FENCODE); however, this is not always possible and the
incomplete settling may degrade the SFDR. The sampling
glitch has been designed to be as linear as possible to
minimize the effects of incomplete settling.
For the best performance, it is recommended to have a
source impedance of 100
or less for each input. The
source impedance should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
Input Drive Circuits
Figure 3 shows the LTC2220/LTC2221 being driven by an
RF transformer with a center tapped secondary. The sec-
ondary center tap is DC biased with VCM, setting the ADC
input signal at its optimum DC level. Terminating on the
transformer secondary is desirable, as this provides a
common mode path for charging glitches caused by the
sample and hold. Figure 3 shows a 1:1 turns ratio trans-
former. Other turns ratios can be used if the source
impedance seen by the ADC does not exceed 100
foreach
ADC input. A disadvantage of using a transformer is the
loss of low frequency response. Most small RF transform-
ers have poor performance at frequencies below 1MHz.
Figure 4 demonstrates the use of a differential amplifier to
convert a single ended input signal into a differential input
signal. The advantage of this method is that it provides low
frequencyinputresponse;however,thelimitedgainbandwidth
of most op amps will limit the SFDR at high input frequencies.
Figure 5 shows a single-ended input circuit. The imped-
ance seen by the analog inputs should be matched. This
circuit is not recommended if low distortion is required.
The 25
resistorsand12pFcapacitorontheanaloginputs
serve two purposes: isolating the drive circuitry from the
sample-and-hold charging glitches and limiting the
wideband noise at the converter input. For input frequen-
cies higher than 100MHz, the capacitor may need to be
decreased to prevent excessive signal loss.
25
25
25
25
0.1
F
AIN
+
AIN
+
AIN
–
AIN
–
12pF
2.2
F
VCM
LTC2220/
LTC2221
ANALOG
INPUT
0.1
FT1
1:1
T1 = MA/COM ETC1-1T
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
22201 F03
Figure 3. Single-Ended to Differential
Conversion Using a Transformer
25
25
AIN
+
AIN
+
AIN
–
AIN
–
12pF
2.2
F
3pF
VCM
LTC2220/
LTC2221
22201 F04
–
+
CM
ANALOG
INPUT
HIGH SPEED
DIFFERENTIAL
AMPLIFIER
AMPLIFIER = LTC6600-20, LT1993, ETC.
Figure 4. Differential Drive with an Amplifier
APPLICATIO S I FOR ATIO
WU
UU
Figure 5. Single-Ended Drive
25
0.1
F
ANALOG
INPUT
VCM
AIN
+
AIN
+
AIN
–
AIN
–
1k
12pF
22201 F05
2.2
F
1k
25
0.1
F
LTC2220/
LTC2221
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