參數(shù)資料
型號(hào)： LTC2220CUP-1#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 13/28頁(yè)
文件大?。?/td> 0K
描述： IC ADC 12BIT 185MSPS 64-QFN
標(biāo)準(zhǔn)包裝： 2,000
位數(shù)： 12
采樣率（每秒）： 185M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 1.18W
電壓電源： 單電源
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 64-WFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 64-QFN（9x9）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 1 個(gè)單端，雙極; 1 個(gè)差分，雙極
20
LTC2220-1
2220_1fa
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2220-1 should drive a minimal
capacitive load to avoid possible interaction between the
digital outputs and sensitive input circuitry. The output
should be buffered with a device such as an ALVCH16373
CMOS latch. For full speed operation the capacitive load
should be kept under 10pF.
Lower OVDD voltages will also help reduce interference
from the digital outputs.
Digital Output Buffers (LVDS Mode)
Figure 13b shows an equivalent circuit for a differential
output pair in the LVDS output mode. A 3.5mA current is
steered from OUT+ to OUT– or vice versa which creates a
±350mV differential voltage across the 100 termination
resistor at the LVDS receiver. A feedback loop regulates
the common mode output voltage to 1.25V. For proper
operation each LVDS output pair needs an external 100
termination resistor, even if the signal is not used (such as
OF+/OF– or CLKOUT+/CLKOUT–). To minimize noise the
PC board traces for each LVDS output pair should be
routed close together. To minimize clock skew all LVDS PC
board traces should have about the same length.
APPLICATIO S I FOR ATIO
WU
UU
Table 3. MODE Pin Function
Clock Duty
MODE Pin
Output Format
Cycle Stablizer
0
Offset Binary
Off
1/3VDD
Offset Binary
On
2/3VDD
2’s Complement
On
VDD
2’s Complement
Off
Data Format
The LTC2220-1 parallel digital output can be selected for
offset binary or 2’s complement format. The format is
selected with the MODE pin. Connecting MODE to GND or
1/3VDD selects offset binary output format. Connecting
MODE to 2/3VDD or VDD selects 2’s complement output
format. An external resistor divider can be used to set the
1/3VDD or 2/3VDD logic values. Table 3 shows the logic
states for the MODE pin.
LTC2220-1
22201 F13b
OVDD
LVDS
RECEIVER
OGND
1.25V
D
OUT+
OUT–
100
+
–
3.5mA
10k
Figure 13b. Digital Output in LVDS Mode
Overflow Bit
An overflow output bit indicates when the converter is
overranged or underranged. In CMOS mode, a logic high
on the OFA pin indicates an overflow or underflow on the
A data bus, while a logic high on the OFB pin indicates an
overflow or underflow on the B data bus. In LVDS mode,
a differential logic high on the OF+/OF– pins indicates an
overflow or underflow.
Output Clock
The ADC has a delayed version of the ENC+ input available
as a digital output, CLKOUT. The CLKOUT pin can be used
to synchronize the converter data to the digital system. This
is necessary when using a sinusoidal encode. In all CMOS
modes, A bus data will be updated just after CLKOUTA rises
and can be latched on the falling edge of CLKOUTA. In demux
CMOS mode with interleaved update, B bus data will be
updated just after CLKOUTB rises and can be latched on the
falling edge of CLKOUTB. In demux CMOS mode with si-
multaneous update, B bus data will be updated just after
CLKOUTB falls and can be latched on the rising edge of
CLKOUTB. In LVDS mode, data will be updated just after
CLKOUT+/CLKOUT– rises and can be latched on the falling
edge of CLKOUT+/CLKOUT–.
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