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參數(shù)資料
| 型號： | LTC2208UP |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 16-Bit, 130Msps ADC |
| 中文描述： | 16位，130Msps ADC |
| 文件頁數(shù)： | 23/32頁 |
| 文件大小： | 1222K |
| 代理商： | LTC2208UP |
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LTC2208
23
2208fa
resistor, even if the signal is not used (such as OF
+
/OF
–
or
CLKOUT
+
/CLKOUT
–
). To minimize noise the PC board
traces for each LVDS output pair should be routed close
together. To minimize clock skew all LVDS PC board traces
should have about the same length.
In Low Power LVDS Mode 1.75mA is steered between
the differential outputs, resulting in ±175mV at the LVDS
receiver’s 100
Ω
termination resistor. The output com-
mon mode voltage is 1.20V, the same as standard LVDS
Mode.
Data Format
The LTC2208 parallel digital output can be selected for
offset binary or 2’s complement format. The format is
selected with the MODE pin. This pin has a four level
logic input, centered at 0, 1/3V
DD
, 2/3V
DD
and V
DD
. An
external resistor divider can be user to set the 1/3V
DD
and 2/3V
DD
logic levels. Table 2 shows the logic states
for the MODE pin.
Table 2. MODE Pin Function
Clock Duty
Cycle Stabilizer
Off
On
On
Off
MODE
0(GND)
1/3V
DD
2/3V
DD
V
DD
Output Format
Offset Binary
Offset Binary
2’s Complement
2’s Complement
LTC2208
2208 F11
OV
DD
V
DD
V
DD
0.1
μ
F
TYPICAL
DATA
OUTPUT
OGND
OV
DD
0.5V
TO 3.6V
PREDRIVER
LOGIC
DATA
FROM
LATCH
Figure 11. Equivalent Circuit for a Digital Output Buffer
APPLICATIU
output may be used but is not required since the ADC has
a series resistor of 43
Ω
on chip.
Lower OV
DD
voltages will also help reduce interference
from the digital outputs.
W
U
U
Digital Output Buffers (LVDS Modes)
Figure 12 shows an equivalent circuit for an LVDS output
pair. A 3.5mA current is steered from OUT
+
to OUT
–
or
vice versa, which creates a ±350mV differential voltage
across the 100
Ω
termination resistor at the LVDS receiver.
A feedback loop regulates the common mode output volt-
age to 1.20V. For proper operation each LVDS output pair
must be terminated with an external 100
Ω
termination
LTC2208
2208 F12
3.5mA
1.20V
LVDS
RECEIVER
OGND
10k
10k
V
DD
V
DD
0.1
μ
F
OV
DD
3.3V
PREDRIVER
LOGIC
DATA
FROM
LATCH
+
–
OV
DD
OV
DD
43
43
100
Figure 12. Equivalent Output Buffer in LVDS Mode
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| LTC2208UP-14 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:14-Bit, 130Msps ADC |
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