參數(shù)資料
型號: LTC2205I#PBF
廠商: LINEAR TECHNOLOGY CORP
元件分類: ADC
英文描述: 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48
封裝: 7 X7 MM, LEAD FREE, PLASTIC, MO-220, QFN-48
文件頁數(shù): 18/28頁
文件大?。?/td> 804K
代理商: LTC2205I#PBF
LTC2205/LTC2204
25
22054p
The digital output is “Randomized” by applying an exclu-
sive-OR logic operation between the LSB and all other data
output bits. To decode, the reverse operation is applied;
that is, an exclusive-OR operation is applied between the
LSB and all other bits. The LSB, OF and CLKOUT output
are not affected. The output Randomizer function is active
when the RAND pin is high.
APPLICATIO S I FOR ATIO
WU
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Data Format
The LTC2205/LTC2204 parallel digital output can be
selected for offset binary or 2’s complement format. The
format is selected with the MODE pin. This pin has a four
level logic input, centered at 0, 1/3VDD, 2/3VDD and VDD.
An external resistor divider can be user to set the 1/3VDD
and 2/3VDD logic levels. Table 1 shows the logic states
for the MODE pin.
Table 1. MODE Pin Function
Clock Duty
MODE
Output Format
Cycle Stabilizer
0(GND)
Straight Binary
Off
1/3VDD
Straight Binary
On
2/3VDD
2’s Complement
On
VDD
2’s Complement
Off
Overow Bit
An overow output bit (OF) indicates when the converter
is over-ranged or under-ranged. A logic high on the OF
pin indicates an overow or underow.
Output Clock
The ADC has a delayed version of the encode input available
as a digital output. Both a noninverted version, CLKOUT+
and an inverted version CLKOUT– are provided. The
CLKOUT+/CLKOUT– can be used to synchronize the con-
verter data to the digital system. This is necessary when
using a sinusoidal encode. Data can be latched on the
rising edge of CLKOUT+ or the falling edge of CLKOUT–.
CLKOUT+ falls and CLKOUT– rises as the data outputs
are updated.
Digital Output Randomizer
Interference from the ADC digital outputs is sometimes
unavoidable. Interference from the digital outputs may be
from capacitive or inductive coupling or coupling through
the ground plane. Even a tiny coupling factor can result in
discernible unwanted tones in the ADC output spectrum.
By randomizing the digital output before it is transmitted
off chip, these unwanted tones can be randomized, trading
a slight increase in the noise oor for a large reduction in
unwanted tone amplitude.
Figure 12. Functional Equivalent of Digital Output Randomizer
CLKOUT
OF
D15/D0
D14/D0
D2/D0
D1/D0
D0
D1
RAND = HIGH,
SCRAMBLE
ENABLED
D2
D14
D15
OF
LTC2205/LTC2204
CLKOUT
RAND
22054 F12
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OVDD, should be tied
to the same power supply as for the logic being driven.
OVDD can be powered with any logic voltage up to the VDD
of the ADC. OGND can be powered with any voltage from
ground up to 1V and must be less than OVDD. The logic
outputs will swing between OGND and OVDD.
相關(guān)PDF資料
PDF描述
LTC2205I#TRPBF 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48
LTC2205I#TR 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48
LTC2205I 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48
LTC2204I#TR 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48
LTC2205C 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48
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