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參數(shù)資料
| 型號： | LTC2204C |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48 |
| 封裝： | 7 X7 MM, PLASTIC, MO-220, QFN-48 |
| 文件頁數(shù)： | 14/28頁 |
| 文件大?。?/td> | 804K |
| 代理商： | LTC2204C |
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LTC2205/LTC2204
21
22054p
the charging glitch seen at the input will be small. If the
input change is large, such as the change seen with input
frequencies near Nyquist, then a larger charging glitch
will be seen.
Common Mode Bias
The ADC sample-and-hold circuit requires differential
drive to achieve specied performance. Each input should
swing ± 0.5625V for the 2.25V range (PGA = 0) or ± 0.375V
for the 1.5V range (PGA = 1), around a common mode
voltage of 1.25V. The VCM output pin (Pin 3) is designed
to provide the common mode bias level. VCM can be tied
directly to the center tap of a transformer to set the DC
input level or as a reference level to an op amp differential
driver circuit. The VCM pin must be bypassed to ground
close to the ADC with 2.2F or greater.
Input Drive Impedence
As with all high performance, high speed ADCs the
dynamic performance of the LTC2205/LTC2204 can be
inuenced by the input drive circuitry, particularly the
second and third harmonics. Source impedance and in-
put reactance can inuence SFDR. At the falling edge of
ENC the sample-and-hold circuit will connect the 4.9pF
sampling capacitor to the input pin and start the sampling
period. The sampling period ends when ENC rises, hold-
ing the sampled input on the sampling capacitor. Ideally,
the input circuitry should be fast enough to fully charge
the sampling capacitor during the sampling period
1/(2FENCODE); however, this is not always possible and the
incomplete settling may degrade the SFDR. The sampling
glitch has been designed to be as linear as possible to
minimize the effects of incomplete settling.
For the best performance it is recomended to have a source
impedence of 100Ω or less for each input. The source
impedence should be matched for the differential inputs.
Poor matching will result in higher even order harmonics,
especially the second.
INPUT DRIVE CIRCUITS
Input Filtering
A rst order RC lowpass lter at the input of the ADC
can serve two functions: limit the noise from input cir-
cuitry and provide isolation from ADC S/H switching. The
LTC2205/LTC2204 have a very broadband S/H circuit, DC
to 700MHz; it can be used in a wide range of applications;
therefore, it is not possible to provide a single recom-
mended RC lter.
Figures 3, 4a and 4b show three examples of input RC
ltering at three ranges of input frequencies. In general
it is desirable to make the capacitors as large as can be
tolerated—this will help suppress random noise as well
as noise coupled from the digital circuitry. The LTC2205/
LTC2204 do not require any input lter to achieve data sheet
specications; however, no ltering will put more stringent
noise requirements on the input drive circuitry.
Transformer Coupled Circuits
Figure 3 shows the LTC2205/LTC2204 being driven by
an RF transformer with a center-tapped secondary. The
secondary center tap is DC biased with VCM, setting the
ADC input signal at its optimum DC level. Figure 3 shows
a 1:1 turns ratio transformer. Other turns ratios can be
used; however, as the turns ratio increases so does the
impedance seen by the ADC. Source impedance greater
than 50Ω can reduce the input bandwidth and increase
high frequency distortion. A disadvantage of using a
transformer is the loss of low frequency response. Most
small RF transformers have poor performance at frequen-
cies below 1MHz.
Center-tapped transformers provide a convenient means
of DC biasing the secondary; however, they often show
poor balance at high input frequencies, resulting in large
2nd order harmonics.
Figure 3. Single-Ended to Differential Conversion
Using a Transformer. Recommended for Input
Frequencies from 5MHz to 50MHz
APPLICATIO S I FOR ATIO
WU
U
25
25
10
10
0.1
F
AIN
+
AIN
–
12pF
2.2
F
12pF
VCM
LTC2205/
LTC2204
ANALOG
INPUT
0.1
FT1
1:1
T1 = MA/COM ETC1-1T
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
EXCEPT 2.2
F
22054 F03
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LTC2204CUK | 制造商:LINER 制造商全稱:Linear Technology 功能描述:16-Bit, 65Msps/40Msps |
| LTC2204CUK#PBF | 制造商:Linear Technology 功能描述:Single ADC Pipelined 40Msps 16-bit Parallel 48-Pin QFN EP 制造商:Linear Technology 功能描述:IC ADC 16-BIT 40MSPS 48-QFN 制造商:Linear Technology 功能描述:MS-ADC/High Speed, 16-bit, 40Msps ADC 制造商:Linear Technology 功能描述:IC, ADC, 16BIT, 40MSPS, QFN-48, Resolution (Bits):16bit, Sampling Rate:40MSPS, Supply Voltage Type:Single, Supply Voltage Min:3.135V, Supply Voltage Max:3.465V, Supply Current:145mA, Digital IC Case Style:QFN, No. of Pins:48 , RoHS Compliant: Yes |
| LTC2204CUK#TRPBF | 制造商:Linear Technology 功能描述:IC ADC 16-BIT 40MSPS 48-QFN |
| LTC2204CUK-PBF | 制造商:LINER 制造商全稱:Linear Technology 功能描述:16-Bit, 65Msps/40Msps |
| LTC2204CUK-TR | 制造商:LINER 制造商全稱:Linear Technology 功能描述:16-Bit, 65Msps/40Msps |
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