參數(shù)資料
型號(hào)： LTC2182IUP#PBF
廠商： LINEAR TECHNOLOGY CORP
元件分類： ADC
英文描述： 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
封裝： 9 X 9 MM, LEAD FREE, PLASTIC, MO-220WNJR-5, QFN-64
文件頁(yè)數(shù)： 14/36頁(yè)
文件大?。?/td> 3836K
代理商： LTC2182IUP#PBF
21
218210f
LTC2182/LTC2181/LTC2180
APPLICATIONS INFORMATION
VREF
REFH
SENSE
C1
TIE TO VDD FOR 2V RANGE;
TIE TO GND FOR 1V RANGE;
RANGE = 1.6 VSENSE FOR
0.625V < VSENSE < 1.300V
1.25V
REFL
INTERNAL ADC
HIGH REFERENCE
BUFFER
218210 F08a
LTC2182
5
0.8x
DIFF AMP
INTERNAL ADC
LOW REFERENCE
C1: 2.2F LOW INDUCTANCE
INTERDIGITATED CAPACITOR
TDK CLLE1AX7S0G225M
MURATA LLA219C70G225M
AVX W2L14Z225M
OR EQUIVALENT
1.25V BANDGAP
REFERENCE
0.625V
RANGE
DETECT
AND
CONTROL
2.2F
C2
0.1F
C3
0.1F
+
–
+
Figure 8a. Reference Circuit
SENSE
1.25V
EXTERNAL
REFERENCE
2.2F
1F
VREF
218210 F09
LTC2182
Figure 9. Using an External 1.25V Reference
REFH
REFL
218210 F08b
LTC2182
CAPACITORS ARE 0402 PACKAGE SIZE
C3
0.1F
C1
2.2F
C2
0.1F
Figure 8b. Alternative REFH/REFL Bypass Circuit
Figure 8c. Recommended Layout for the REFH/REFL
Bypass Circuit in Figure 8a
Alternatively C1 can be replaced by a standard 2.2F
capacitor between REFH and REFL (see Figure 8b). The
capacitors should be as close to the pins as possible (not
on the back side of the circuit board).
Figure 8c and Figure 8d show the recommended circuit
board layout for the REFH/REFL bypass capacitors. Note
that in Figure 8c, every pin of the interdigitated capacitor
(C1)isconnectedsincethepinsarenotinternallyconnected
in some vendors’ capacitors. In Figure 8d the REFH and
Figure 8d. Recommended Layout for the REFH/REFL
Bypass Circuit in Figure 8b
Encode Inputs
The signal quality of the encode inputs strongly affects
the A/D noise performance. The encode inputs should
be treated as analog signals – do not route them next to
digital traces on the circuit board. There are two modes
of operation for the encode inputs: the differential encode
mode (Figure 10), and the single-ended encode mode
(Figure 11).
The differential encode mode is recommended for si-
nusoidal, PECL, or LVDS encode inputs (Figure 12 and
Figure 13). The encode inputs are internally biased to 1.2V
through 10k equivalent resistance. The encode inputs
can be taken above VDD (up to 3.6V), and the common
mode range is from 1.1V to 1.6V. In the differential encode
REFL pins are connected by short jumpers in an internal
layer. To minimize the inductance of these jumpers they
can be placed in a small hole in the GND plane on the
second board layer.
相關(guān)PDF資料
PDF描述
LTC2181IUP#PBF 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
LTC2181IUP#TRPBF 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
LTC2180IUP#PBF 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
LTC2180IUP#TRPBF 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
LTC2180CUP#PBF 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LTC2183 制造商:LINER 制造商全稱:Linear Technology 功能描述:16-Bit, 125/105/80Msps Low Power Dual ADCs
LTC2183CUP#PBF 制造商:Linear Technology 功能描述:ADC Dual 80Msps 16-bit Parallel/Serial (SPI)/LVDS 64-Pin QFN EP 制造商:Linear Technology 功能描述:IC ADC 16BIT PAR/SRL 80M 64-QFN
LTC2183CUP#PBF-ES 制造商:Linear Technology 功能描述:ADC Dual 80Msps 16-bit Parallel/Serial (SPI)/LVDS 64-Pin QFN EP
LTC2183CUP#TRPBF 制造商:Linear Technology 功能描述:ADC Dual 80Msps 16-bit Parallel/Serial (SPI)/LVDS 64-Pin QFN EP T/R 制造商:Linear Technology 功能描述:IC ADC 16BIT PAR/SRL 80M 64-QFN
LTC2183CUP#TRPBF-ES 制造商:Linear Technology 功能描述:ADC Dual 80Msps 16-bit Parallel/Serial (SPI)/LVDS 64-Pin QFN EP T/R
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