參數(shù)資料
型號(hào)： LTC2182CUP#TRPBF
廠商： LINEAR TECHNOLOGY CORP
元件分類(lèi)： ADC
英文描述： 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
封裝： 9 X 9 MM, LEAD FREE, PLASTIC, MO-220WNJR-5, QFN-64
文件頁(yè)數(shù)： 34/36頁(yè)
文件大?。?/td> 3836K
代理商： LTC2182CUP#TRPBF
7
218210f
LTC2182/LTC2181/LTC2180
POWER REQUIREMENTS The
l
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL PARAMETER
CONDITIONS
LTC2182
LTC2181
LTC2180
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
CMOS Output Modes: Full Data Rate and Double Data Rate
VDD
Analog Supply Voltage (Note 10)
l
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
V
OVDD
Output Supply Voltage
(Note 10)
l
1.1
1.8
1.9
1.1
1.8
1.9
1.1
1.8
1.9
V
IVDD
Analog Supply Current DC Input
Sine Wave Input
l
89
91
99
64
66
72
43.5
44.5
50
mA
IOVDD
Digital Supply Current
Sine Wave Input, OVDD = 1.2V
5
3
2
mA
PDISS
Power Dissipation
DC Input
Sine Wave Input, OVDD = 1.2V
l
160
170
179
115
122
130
78.3
82.5
90
mW
LVDS Output Mode
VDD
Analog Supply Voltage (Note 10)
l
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
V
OVDD
Output Supply Voltage
(Note 10)
l
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
V
IVDD
Analog Supply Current Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
l
93
95
106
68
70
77
46.5
48.5
54
mA
IOVDD
Digital Supply Current
(0VDD = 1.8V)
Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
l
39
74
83
38
74
83
38
74
83
mA
PDISS
Power Dissipation
Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
l
237
304
341
191
259
288
152
221
247
mW
All Output Modes
PSLEEP
Sleep Mode Power
1
mW
PNAP
Nap Mode Power
10
mW
PDIFFCLK Power Increase with Differential Encode Mode Enabled
(No increase for Nap or Sleep Modes)
20
mW
TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
LTC2182
LTC2181
LTC2180
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
fS
Sampling Frequency
(Note 10)
l
1
65
1
40
1
25
MHz
tL
ENC Low Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
7.3
2
7.69
500
11.88
2
12.5
500
19
2
20
500
ns
tH
ENC High Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
7.3
2
7.69
500
11.88
2
12.5
500
19
2
20
500
ns
tAP
Sample-and-Hold
Acquisition Delay Time
0
ns
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Digital Data Outputs (CMOS Modes: Full Data Rate and Double Data Rate)
tD
ENC to Data Delay
CL = 5pF (Note 8)
l
1.1
1.7
3.1
ns
tC
ENC to CLKOUT Delay
CL = 5pF (Note 8)
l
1
1.4
2.6
ns
tSKEW
DATA to CLKOUT Skew
tD – tC (Note 8)
l
0
0.3
0.6
ns
Pipeline Latency
Full Data Rate Mode
Double Data Rate Mode
6
6.5
Cycles
相關(guān)PDF資料
PDF描述
LTC2182IUP#TRPBF 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
LTC2181CUP#PBF 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
LTC2181CUP#TRPBF 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
LTC2180CUP#TRPBF 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
LTC2185CUP#PBF 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LTC2182IUP#PBF 制造商:Linear Technology 功能描述:ADC Dual 65Msps 16-bit Parallel/Serial (SPI)/LVDS 64-Pin QFN EP 制造商:Linear Technology 功能描述:IC ADC 16BIT DUAL PAR/SRL 64QFN
LTC2182IUP#PBF-ES 制造商:Linear Technology 功能描述:ADC Dual 65Msps 16-bit Parallel/Serial (SPI)/LVDS 64-Pin QFN EP
LTC2182IUP#TRPBF 制造商:Linear Technology 功能描述:ADC Dual 65Msps 16-bit Parallel/Serial (SPI)/LVDS 64-Pin QFN EP T/R 制造商:Linear Technology 功能描述:IC ADC DUAL 16BIT 65MSPS 64-QFN
LTC2182IUP#TRPBF-ES 制造商:Linear Technology 功能描述:ADC Dual 65Msps 16-bit Parallel/Serial (SPI)/LVDS 64-Pin QFN EP T/R
LTC2183 制造商:LINER 制造商全稱(chēng):Linear Technology 功能描述:16-Bit, 125/105/80Msps Low Power Dual ADCs
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